Memory system for writing data based on types of command and data and operating method of the same

Patent metadata

Field	Value
Publication number	US-10528469-B2
Application number	US-201715672826-A
Country	US
Kind code	B2
Filing date	Aug 9, 2017
Priority date	Jan 12, 2017
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

An memory system includes a memory device that includes a first memory block and a super memory block including simultaneously controllable second memory blocks and a controller including a memory, and suitable for storing a data corresponding to a command in the memory, deciding a type of the command and a type of the data, and controlling the memory device to write the data in the first memory block or the super memory block based on the type of the command and the type of the data.

First claim

What is claimed is:

1. A memory system comprising:
a memory device including a first memory block group and a second memory block group, where each of the first and second memory block groups includes memory blocks from each of a plurality of memory dies; and
a controller suitable for performing a first program operation of programming data having units of a page into a single memory block among memory blocks included in the first memory block group in a one-shot program operation, performing a second program operation of programming data having units of super-blocks into memory blocks included in the second memory block group in an interleaving manner, and selectively performing the first and second memory program operations according to a type of a command and a type of the data,
wherein the controller performs the first program operation when the type of the command is a Force Unit Access (FUA) command and the type of data is a random data, and
wherein the controller performs the second program operation when the type of the command is a cache flush command and the type of the data is a sequential data.

2. The memory system of claim 1 , wherein when a size of data, stored in a write buffer at the moment that the cache flush command is issued, is less than the units of the super-blocks, the controller performs the second program operation by adding dummy data to all of the data stored in the write buffer.

3. The memory system of claim 1 , wherein when a size of data corresponding to the FUA command is less than the units of the page, the controller instantly performs the first program operation in response to the FUA command by adding dummy data to the data corresponding to the FUA command.

4. The memory system of claim 1 , wherein when a size of the random data is less than the units of the page, the controller performs the first program operation by adding dummy data to the random data.

5. The memory system of claim 1 , wherein when a size of the sequential data is less than the units of the super-blocks, the controller waits until a size of data stored in a write buffer reaches the units of the super-blocks and then performs the second program operation.

6. An operating method of a memory system, the operating method comprising:
performing a first program operation of programming data having units of a page into a single memory block among memory blocks included in a first memory block group in a one-shot program operation, where the first memory block group includes memory blocks from each of a plurality of memory dies;
performing a second program operation of programming data having units of super-blocks into memory blocks included in a second memory block group in an interleaving manner, where the second memory block group includes memory blocks from each of the memory dies; and
selectively performing the first and second program operations according to a type of a command and a type of the data,
wherein the first program operation is performed when the type of the command is a Force Unit Access (FUA) command and the type of data is a random data, and
wherein the second program operation is performed when the type of command is a cache flush command and the type of the data is sequential data.

7. The method of claim 6 , wherein when a size of data stored in a write buffer at the moment that the cache flush command is issued is less than the units of the super-blocks, the second program operation is performed by adding dummy data to all of the data stored in the write buffer.

8. The method of claim 6 , wherein when a size of data corresponding to the FUA command is less than the units of the page, the first program operation is instantly performed in response to the FUA command by adding dummy data to the data corresponding to the FUA command.

9. The method of claim 6 , wherein when a size of the random data is less than the units of the page, the first program operation is performed by adding dummy data to the random data.

10. The method of claim 6 , wherein when a size of the sequential data is less than the units of the super-blocks, the second program operation is performed after a size of data stored in a write buffer reaches the units of the super-blocks.

Assignees

• Sk Hynix Inc

Inventors

• Koo Duck-Hoi
• SHIN Soong-Sun

Classifications

• G11C2207/2245

  Memory devices with an internal cache buffer · CPC title

• G06F2212/7203

  Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title

• G06F3/0667

  at data level, e.g. file, record or object virtualisation · CPC title

• G06F12/0866

  for peripheral storage systems, e.g. disk cache · CPC title

• G06F3/064 Primary

  Management of blocks · CPC title