Semiconductor device with multichannel heterostructure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12317569-B2
Application number	US-202418646773-A
Country	US
Kind code	B2
Filing date	Apr 26, 2024
Priority date	Apr 22, 2020
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional hole gas (2DHG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different first semiconductor material layer and is in contact with the 2DHG.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a semiconductor heterostructure layer, comprising alternating first semiconductor material layers and second semiconductor material layers, wherein a two-dimensional hole gas (2DHG) is generated between each first semiconductor material layer and its above adjacent second semiconductor material layer;
a first electrode structure, comprising a plurality of first conductive fingers extending from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer, wherein the plurality of first conductive fingers are arranged in a first direction substantially parallel to the surface, and wherein lengths of the plurality of first conductive fingers progressively increase in the first direction so that an end portion of each first conductive finger is respectively positioned in a different first semiconductor material layer and is in contact with the 2DHGs;
a second electrode structure, comprising a plurality of second conductive fingers extending from the surface into the semiconductor heterostructure layer, wherein the plurality of second conductive fingers are arranged in the first direction, and wherein lengths of the plurality of second conductive fingers progressively decrease in the first direction so that an end portion of each second conductive finger is respectively positioned in a different second semiconductor material layer and is not in contact with the 2DHGs.

2. The semiconductor device of claim 1 , wherein widths of the plurality of the first conductive fingers gradually increase in the first direction, and widths of the plurality of the second conductive fingers gradually decrease in the first direction.

3. The semiconductor device of claim 1 , wherein a combination of the first semiconductor material layers and the second semiconductor material layers is one of the following: a combination of AlGaN and GaN, a combination of InAlN and GaN, a combination of AlN and GaN, and a combination of InAlGaN and GaN.

4. The semiconductor device according to claim 1 , wherein the first direction is a direction in which electron holes flow in the 2DHG, or opposite that in which electron holes flow in the 2DHG.

5. The semiconductor device according to claim 1 , wherein a number of layers of the 2DHGs between the first semiconductor material layers and the second semiconductor material layers is in a range of 2 to 10.

6. The semiconductor device according to claim 1 , wherein a thickness of each first semiconductor material layer is in a range of 2 nm to 30 nm.

7. The semiconductor device according to claim 6 , wherein the thickness of each first semiconductor material layer is in a range of 3 nm to 10 nm.

8. The semiconductor device according to claim 1 , wherein a thickness of each second semiconductor material layer is in a range of 2 nm to 70 nm.

9. The semiconductor device according to claim 8 , wherein the thickness of each second semiconductor material layer is in a range of 3 nm to 20 nm.

10. The semiconductor device according to claim 1 , wherein a thickness of the semiconductor heterostructure layer is in a range of 8 nm to 1000 nm.

11. The semiconductor device according to claim 1 , wherein the lengths of the first and second conductive fingers are in a range of 1 nm to 1000 nm.

12. The semiconductor device according to claim 11 , wherein the lengths of the first and second conductive fingers are in a range of 1 nm to 300 nm.

13. The semiconductor device according to claim 1 , wherein widths of the first and second conductive fingers are in a range of 5 nm to 800 nm.

14. The semiconductor device according to claim 13 , wherein the widths of the first and second conductive fingers are in a range of 5 nm to 200 nm.

15. A method for manufacturing a semiconductor device, comprising:
forming a semiconductor heterostructure layer, comprising alternately forming first semiconductor material layers and second semiconductor material layers, wherein a two-dimensional hole gas (2DHG) is generated between each first semiconductor material layer and its above adjacent second semiconductor material layer; and
etching the semiconductor heterostructure layer to form a plurality of trenches in the semiconductor heterostructure layer along a first direction substantially parallel to a surface of the semiconductor heterostructure layer, wherein depths of the plurality of trenches progressively increase in the first direction, the etching stops in different first semiconductor material layers, and a bottom of each trench is in contact with the 2DHG; and
depositing a conductive material in the plurality of trenches so as to form a conductive structure.

16. The method for manufacturing a semiconductor device according to claim 15 , wherein widths of the plurality of trenches progressively increase in the first direction.

17. The method for manufacturing a semiconductor device according to claim 16 , wherein the widths of the plurality of trenches are designed so that the plurality of trenches with different depths are formed in one etching step.

18. The method for manufacturing a semiconductor device according to claim 15 , further comprising:
forming a buffer layer on a carrier; and
forming the semiconductor heterostructure layer on the buffer layer.

Assignees

• Innoscience Zhuhai Technology Co Ltd

Inventors

• Zhang Anbang
• Wong King Yuen
• Li Hao
• Zheng Haoning
• Wang Jian

Classifications

• H10D64/256 Primary

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/8503 Primary

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D30/637

  Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title

• H10D30/475

  having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs · CPC title