Semiconductor device and manufacturing method of the same

Patent metadata

Field	Value
Publication number	US-9685445-B2
Application number	US-201514732984-A
Country	US
Kind code	B2
Filing date	Jun 8, 2015
Priority date	May 16, 2012
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A semiconductor device includes a buffer layer formed with a semiconductor adapted to produce piezoelectric polarization, and a channel layer stacked on the buffer layer, wherein a two-dimensional hole gas, generated in the channel layer by piezoelectric polarization of the buffer layer, is used as a carrier of the channel layer. On a complementary semiconductor device, the semiconductor device described above and an n-type field effect transistor are formed on the same compound semiconductor substrate. Also, a level shift circuit is manufactured by using the semiconductor device. Further, a semiconductor device manufacturing method includes forming a compound semiconductor base portion, forming a buffer layer on the base portion, forming a channel layer on the buffer layer, forming a gate on the channel layer, and forming a drain and source with the gate therebetween on the channel layer.

First claim

What is claimed is:

1. A complementary semiconductor device, comprising:
a semiconductor device and an n-type field effect transistor on a same compound semiconductor substrate,
wherein the semiconductor device comprises:
a buffer layer that includes a semiconductor configured to produce piezoelectric polarization; and
a channel layer stacked on the buffer layer,
wherein a two-dimensional hole gas, generated in the channel layer by the piezoelectric polarization of the buffer layer, is a carrier of the channel layer,
wherein a semiconductor layer of GaAlInP is stacked between the buffer layer and the compound semiconductor substrate.

2. The complementary semiconductor device of claim 1 , wherein the semiconductor device is a p-type field effect transistor.

3. The complementary semiconductor device of claim 1 , wherein the compound semiconductor substrate is a GaAs single crystal substrate.

4. The complementary semiconductor device of claim 1 , wherein the semiconductor configured to produce the piezoelectric polarization in the buffer layer is InGaP.

5. The complementary semiconductor device of claim 1 , wherein the semiconductor configured to produce the piezoelectric polarization in the buffer layer is pure InGaP.

6. The complementary semiconductor device of claim 1 ,
wherein the buffer layer is between the channel layer and a schottky layer,
wherein the buffer layer includes a semiconductor layer that buffer a difference in lattice constant between the channel layer and the schottky layer.

7. The complementary semiconductor device of claim 1 , wherein the channel layer includes at least one of a GaAs layer, an InGaAs layer, an AlGaAs layer or an InGaAsP layer, wherein no impurity is added to the one or more layers of the channel layer.

8. The complementary semiconductor device of claim 1 , wherein the channel layer includes a semiconductor having a higher energy level of the valence band than the buffer layer.

9. The complementary semiconductor device of claim 1 , wherein the channel layer includes a semiconductor that lattice-matches the semiconductor configured to produce the piezoelectric polarization of the buffer layer.

10. The complementary semiconductor device of claim 1 , wherein the channel layer includes a semiconductor doped with C, Zn or Be as an impurity at a concentration of 1×10 17 atoms/cm 3 or less.

11. The complementary semiconductor device of claim 1 , wherein the semiconductor device comprises an n-type first gate layer and an n-type second gate layer stacked, on the channel layer, in an order from a side of the compound semiconductor substrate.

12. The complementary semiconductor device of claim 1 , wherein the channel layer includes an AlGaAs layer and an InGaAsP layer, wherein no impurity is added to the AlGaAs layer and the InGaAsP layer.

Assignees

• Sony Corp

Inventors

• Mitsunaga Masahiro

Classifications

• H10D64/011 Primary

  of electrodes ohmically coupled to a semiconductor · CPC title

• H01L29/7785

  Electricity · mapped topic

• H01L29/778

  Electricity · mapped topic

• H01L29/66462

  Electricity · mapped topic

• H01L41/0815

  Electricity · mapped topic