Semiconductor device and manufacturing method of the same

Patent metadata

Field	Value
Publication number	US-10629598-B2
Application number	US-201816161956-A
Country	US
Kind code	B2
Filing date	Oct 16, 2018
Priority date	May 16, 2012
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

A semiconductor device includes a buffer layer formed with a semiconductor adapted to produce piezoelectric polarization, and a channel layer stacked on the buffer layer, wherein a two-dimensional hole gas, generated in the channel layer by piezoelectric polarization of the buffer layer, is used as a carrier of the channel layer. In a complementary semiconductor device, the semiconductor device described above and an n-type field effect transistor are formed on the same compound semiconductor substrate. Further, a semiconductor device manufacturing method includes forming a compound semiconductor base portion, forming a buffer layer on the base portion, forming a channel layer on the buffer layer, forming a gate on the channel layer, and forming a drain and source with the gate therebetween on the channel layer.

First claim

What is claimed is:

1. A complementary semiconductor device, comprising:
a compound semiconductor substrate;
a semiconductor device and an n-type field effect transistor on the compound semiconductor substrate, wherein the semiconductor device comprises:
a buffer layer, wherein the buffer layer includes:
a first semiconductor configured to produce piezoelectric polarization; and
a plurality of first semiconductor layers that lattice-match between each of the plurality of first semiconductor layers; and

a channel layer stacked on the buffer layer,
wherein a second semiconductor layer of Gallium Aluminum Indium Phosphide (GaAlInP) is stacked between the buffer layer and the compound semiconductor substrate.

2. The complementary semiconductor device of claim 1 , wherein the semiconductor device is a p-type field effect transistor.

3. The complementary semiconductor device of claim 1 , wherein the compound semiconductor substrate is a Gallium Arsenide (GaAs) single crystal substrate.

4. The complementary semiconductor device of claim 1 , wherein the first semiconductor configured to produce the piezoelectric polarization in the buffer layer is Indium Gallium Phosphide (InGaP).

5. The complementary semiconductor device of claim 1 , wherein the first semiconductor configured to produce the piezoelectric polarization in the buffer layer is Indium Gallium Phosphide (InGaP) with no impurity.

6. The complementary semiconductor device of claim 1 , wherein
the semiconductor device further comprises a Schottky layer,
the buffer layer is between the channel layer and the Schottky layer,
buffer layer includes a third semiconductor layer, and
the third semiconductor layer buffers a difference in a lattice constant between the channel layer and the Schottky layer.

7. The complementary semiconductor device of claim 1 , wherein
the channel layer includes at least one of a Gallium Arsenide (GaAs) layer, an Indium Gallium Arsenide (InGaAs) layer, an Aluminum Gallium Arsenide (AlGaAs) layer, or an Indium Gallium Arsenide Phosphide (InGaAsP) layer, and
no impurity is added to each of the GaAs layer, InGaAs layer, AlGaAs layer, and the InGaAsP layer.

8. The complementary semiconductor device of claim 1 , wherein the channel layer includes a second semiconductor that has a higher energy level of a valence band than the buffer layer.

9. The complementary semiconductor device of claim 1 , wherein the channel layer includes a second semiconductor that lattice-matches the first semiconductor configured to produce the piezoelectric polarization of the buffer layer.

10. The complementary semiconductor device of claim 1 , wherein the channel layer includes a second semiconductor doped with Carbon (C), Zinc (Zn), or Beryllium (Be) as an impurity at a concentration of 1×10 17 atoms/cm 3 or less.

11. The complementary semiconductor device of claim 1 , wherein the semiconductor device further comprises a stack of an n-type first gate layer and an n-type second gate layer on the channel layer in an order from a side of the compound semiconductor substrate.

12. The complementary semiconductor device of claim 1 , wherein
the channel layer includes an Aluminum Gallium Arsenide (AlGaAs) layer and an Indium Gallium Arsenide Phosphide layer, and
no impurity is added to the AlGaAs layer and the InGaAsP layer.

13. The complementary semiconductor device of claim 1 , wherein a two-dimensional hole gas in the channel layer is a carrier of the channel layer.

14. The complementary semiconductor device of claim 13 , wherein an amount of the two-dimensional hole gas in the channel layer is proportional to a thickness of the buffer layer.

15. The complementary semiconductor device of claim 1 , wherein the buffer layer includes a second semiconductor doped with Carbon (C), Zinc (Zn), or Beryllium (Be) as an impurity at a concentration of 1×10 12 to 4×10 18 atoms/cm 3 .

16. The complementary semiconductor device of claim 1 , wherein the second semiconductor layer of GaAllnP has a band gap different from the first semiconductor and a second semiconductor of the compound semiconductor substrate.

Assignees

• Sony Corp

Inventors

• Mitsunaga Masahiro

Classifications

• H10D64/011 Primary

  of electrodes ohmically coupled to a semiconductor · CPC title

• H01L29/205

  Electricity · mapped topic

• H01L21/8252

  Electricity · mapped topic

• H01L29/66462

  Electricity · mapped topic

• H01L29/7781

  Electricity · mapped topic