Memory device and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-12315802-B2
Application number	US-202318382251-A
Country	US
Kind code	B2
Filing date	Oct 20, 2023
Priority date	Oct 9, 2020
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

A memory device includes a stack structure and a first beam structure. The memory device includes array regions and an intermediate region arranged between the array regions in a first lateral direction. The stack structure includes a first block and a second block arranged in a second lateral direction. Each of the first block and the second block includes a wall-structure region. In the intermediate region, the wall-structure regions of the first block and the second block are separated by a staircase structure. The first beam structure is located in the intermediate region and extends along the second lateral direction. The first beam structure is connected to the wall-structure regions of the first block and the second block. The first beam structure includes first dielectric layers and electrode layers that are alternately stacked.

First claim

What is claimed is:

1. A memory device, comprising:
a stack structure, wherein:
the memory device includes array regions and an intermediate region arranged between the array regions in a first lateral direction; and
the stack structure includes a first block and a second block arranged in a second lateral direction, each of the first block and the second block includes a wall-structure region, wherein in the intermediate region, the wall-structure regions of the first block and the second block are separated by a staircase structure; and

a first beam structure, located in the intermediate region and extending along the second lateral direction, wherein the first beam structure is connected to the wall-structure regions of the first block and the second block, and the first beam structure includes first dielectric layers and electrode layers that are alternately stacked.

2. The memory device according to claim 1 , wherein the first beam structure further includes second dielectric layers that are alternately stacked with the first dielectric layers.

3. The memory device according to claim 2 , further comprising:
a second beam structure, disposed across the first block and the second block and extending through the intermediate region in the first lateral direction, wherein the second beam structure includes the second dielectric layers and the first dielectric layers that are alternately stacked.

4. The memory device according to claim 1 , wherein the array regions, the staircase structure and the wall-structure regions all include the first dielectric layers and the electrode layers that are alternately stacked.

5. The memory device according to claim 2 , further including:
a first isolation structure, formed vertically through the stack structure on each side of the intermediate region along the first lateral direction and between the first block and the second block along the second lateral direction, wherein the first isolation structure comprises silicon oxide.

6. The memory device according to claim 1 , wherein along the first lateral direction, the staircase structure includes a plurality of sub-staircase structures, and adjacent sub-staircase structures are separated by the first beam structure.

7. The memory device according to claim 6 , further including:
a first separation structure, formed vertically through the stack structure and positioned between the first block and the second block in each array region along the first lateral direction, wherein the first block includes a first edge opposite to the second block, and the second block includes a second edge opposite to the first block; and
a second separation structure formed on each of the first edge and the second edge and extending through the array regions and the intermediate region.

8. The memory device according to claim 7 , wherein each of the first block and the second block further includes:
a plurality of fingers, extending along the first lateral direction, wherein:
in the second lateral direction, the plurality of fingers of the first block and the plurality of fingers of the second block are located between; and

the memory device further includes a plurality of third separation structures formed within each of the first block and the second block and between the wall-structure region and an adjacent finger, wherein:
in each array region of the first block or the second block, a third separation structure extends through the array region; and
in the intermediate region of the first block or the second block, a third separation structure is disposed at an edge of each sub-staircase structure close to the wall-structure region, wherein a length of the third separation structure is shorter than or equal to a width of the sub-staircase structure.

9. The memory device according to claim 8 , wherein:
within the first block or the second block, each sub-staircase structure includes a plurality of stairs formed in a finger adjacent to the wall-structure region; and
the memory device further includes a plurality of word line contacts formed in the finger adjacent to the wall-structure region to electrically connect the plurality of stairs.

10. The memory device according to claim 9 , further including:
a plurality of fourth separation structures formed within each of the first block and the second block and between adjacent fingers, wherein:
in each array region of the first block or the second block, a fourth separation structure extends through the array region; and
in the intermediate region of the first block or the second block and between adjacent fingers, a fourth separation structure is disposed in each sub-staircase structure, wherein a length of the fourth separation structure is shorter than or equal to a width of the sub-staircase structure.

11. The memory device according to claim 10 , wherein:
within the first block or the second block, each sub-staircase structure includes a plurality of stairs formed in each finger of the plurality of fingers; and
the memory device further includes a plurality of word line contacts formed in each finger of the plurality of fingers to electrically connect the plurality of stairs.

12. The memory device according to claim 5 , further including:
a plurality of second isolation structures formed between the first block and the second block along the first lateral direction, wherein the second dielectric layers connect adjacent second isolation structures and connect the first isolation structure to the second isolation structure.

13. A memory device, comprising:
a stack structure, wherein:
the memory device includes array regions and an intermediate region arranged between the array regions in a first lateral direction; and
the stack structure includes a first block and a second block arranged in a second lateral direction, each of the first block and the second block includes a wall-structure region, wherein in the intermediate region, the wall-structure regions of the first block and the second block are separated by a staircase structure; and

a first beam structure, located in the intermediate region and extending along the second lateral direction, wherein the first beam structure is connected to the wall-structure regions of the first block and the second block, and the first beam structure includes first dielectric layers and second dielectric layers that are alternately stacked.

14. The memory device according to claim 13 , further comprising:
a second beam structure, disposed across the first block and the second block and extending through the intermediate region in the first lateral direction, wherein the second beam structure includes the second dielectric layers and the first dielectric layers that are alternately stacked.

15. The memory device according to claim 13 , wherein the array regions, the staircase structure, and the wall-structure regions all include the first dielectric layers and electrode layers that are alternately stacked, wherein the second dielectric layer of the first beam structure is in contact with the electrode layer.

16. The memory device according to claim 13 , wherein along the first lateral direction, the staircase structure includes a first sub-staircase structure and a second sub-staircase structure adjacent to the first sub-staircase structure, wherein the first sub-staircase structure and the second sub-staircase structure are separated by the first beam structure.

17. The memory device of claim 1 , wherein:
in the second lateral direction, a gate line slit (GLS) is arranged between t

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zhang Zhong
• Zhang Kun
• Zhou Wenxi
• Xia Zhiliang

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title