Set of stepped surfaces formation for a multilevel interconnect structure

Patent metadata

Field	Value
Publication number	US-9728499-B2
Application number	US-201414554685-A
Country	US
Kind code	B2
Filing date	Nov 26, 2014
Priority date	Nov 26, 2014
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A trench can be formed through a stack of alternating plurality of first material layers and second material layers. A dielectric material liner and a trench fill material portion can be formed in the trench. The dielectric material liner and portions of first material layer can be simultaneously etched to form laterally-extending cavities having level-dependent lateral extents. A set of stepped surfaces can be formed by removing unmasked portions of the second material layers. Alternately, an alternating sequence of processing steps including vertical etch processes and lateral recess processes can be employed to laterally recess second material layers and to form laterally-extending cavities having level-dependent lateral extents. Lateral cavities can be simultaneously formed in multiple levels such that levels having laterally-extending cavities of a same lateral extent are offset across multiple integrated cavities.

First claim

What is claimed is:

1. A method of forming a three-dimensional structure, comprising:
forming a stack comprising a plurality of first material layers and a plurality of second material layers, wherein individual first and second material layers alternate in the stack;
forming a trench vertically extending through at least one second material layer;
laterally recessing each of the at least one second material layer from the trench; and
repeatedly performing a set of processing steps that includes:
a first processing step of vertically extending the trench through at least one additional first material layer and at least one additional second material layer;
a second processing step of laterally recessing each second material layer that is physically exposed in the trench or in a laterally-extending cavity adjoined to the trench;

forming a first integrated dielectric structure by depositing a dielectric material within the trench and the laterally-extending cavities after repeated performance of the set of processing steps; and
replacing portions of the second material layers with a plurality of electrically conductive layers after formation of the integrated dielectric structure.

2. The method of claim 1 , wherein:
the first integrated dielectric structure comprises a dielectric pillar and horizontal dielectric fins that are vertically spaced apart and adjoined to the dielectric pillar;
the horizontal dielectric fins include multiple sets of vertically neighboring horizontal dielectric fins;
vertically neighboring horizontal dielectric fins within a same set among the multiple sets laterally extend by a same lateral distance from the dielectric pillar;
for any pair of an overlying set of vertically neighboring horizontal dielectric fins and an underlying set of vertically neighboring horizontal dielectric fins among the multiple sets, the overlying set of vertically neighboring horizontal dielectric fins laterally protrudes farther than the underlying set of vertically neighboring horizontal dielectric fins; and
sidewalls of the plurality of electrically conductive layers contact sidewalls of the horizontal dielectric fins.

3. The method of claim 1 , further comprising forming a plurality of conductive via structures through the horizontal dielectric fins of the first integrated dielectric structure and directly on the plurality of electrically conductive layers.

4. The method of claim 3 , further comprising:
forming a second integrated dielectric structure comprising a second dielectric pillar and additional horizontal dielectric fins that are vertically spaced apart and adjoined to the second dielectric pillar;
forming a first array of contact via structures through the first integrated dielectric structure, wherein each contact via structure in the first array passes through only a single horizontal dielectric fin or an odd number of horizontal dielectric fins; and
forming a second array of contact via structures through the second integrated dielectric structure, wherein each contact via structure in the second array passes through an even number of additional horizontal dielectric fins.

5. A method of forming a three-dimensional structure, comprising:
forming a stack comprising a plurality of first material layers and a plurality of second material layers, wherein individual first and second material layers alternate in the stack;
forming a trench vertically extending through at least one second material layer;
laterally recessing each of the at least one second material layer from the trench;
repeatedly performing a set of processing steps that includes:
a first processing step of vertically extending the trench through at least one additional first material layer and at least one additional second material layer; and
a second processing step of laterally recessing each second material layer that is physically exposed in the trench or in a laterally-extending cavity adjoined to the trench;

forming a device on the substrate, wherein the device comprises a vertical NAND device; and
replacing portions of the second material layer with a plurality electrically conductive layers, wherein at least one of the plurality of electrically conductive layers comprises, or is electrically connected to, a word line of the vertical NAND device.

6. The method of claim 5 , wherein:
the vertical NAND device comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate;
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level;
the electrically conductive layers in the stack comprise, or are in electrical contact with, the plurality of control gate electrodes and extends from the device region to a contact region containing the plurality of electrically conductive via connections; and
the substrate comprises a silicon substrate containing a driver circuit for the vertical NAND device.

7. A method of forming a three-dimensional structure, comprising:
forming a stack including an alternating plurality of separator layers and interlayers on a substrate;
exposing a first sidewall of a first interlayer located between first and second separator layers without exposing a second sidewall of a second interlayer that is located below the first and second separator layers and above a third separator layer;
laterally recessing the first interlayer without etching the second interlayer;
exposing the second sidewall of the second interlayer without exposing a third sidewall of a third interlayer;
laterally recessing the first and second interlayers simultaneously, wherein exposing the second sidewall and laterally recessing the first and second interlayers simultaneously are performed during separate processing steps employing different etch processes; and
forming an integrated dielectric structure comprising a dielectric pillar and horizontal dielectric fins that are vertically spaced apart and adjoined to the dielectric pillar by filling the trench and recessed volumes of the interlayers with a dielectric material,

wherein the method comprises at least one feature selected from:
a first feature that the horizontal dielectric fins include multiple sets of vertically neighboring horizontal dielectric fins, vertically neighboring horizontal dielectric fins within a same set among the multiple sets laterally extend by a same lateral distance from the dielectric pillar, and, for any pair of an overlying set of vertically neighboring horizontal dielectric fins and an underlying set of vertically neighboring horizontal dielectric fins among the multiple sets, the overlying set of vertically neighboring horizontal dielectric fins laterally protrudes farther than the underlying set of vertically neighboring horizontal dielectric fins; and
a second feature that the method further comprises a step of replacing remaining portions of the interlayer layers with electrically conductive layers after formation of the integrated dielectric structure.

8. The method of claim 7 , wherein the first interlayer is laterally recessed to a greater lateral extent than the second interlayer.

9. The method of claim 7 , further comprising repeatedly performing a set o

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Shimabukuro Seiji
• Iuchi Hiroaki
• Sano Michiaki
• Takeguchi Naoki

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/031 Primary

  of conductive parts of the interconnections · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H01L23/5226 Primary

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic