Vertical antifuse structures

Patent metadata

Field	Value
Publication number	US-9917090-B1
Application number	US-201615243491-A
Country	US
Kind code	B1
Filing date	Aug 22, 2016
Priority date	Aug 22, 2016
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

Semiconductor devices and methods are provided in which vertical antifuse devices are integrally formed with vertical FET devices, wherein the vertical antifuse devices are formed as part of a process flow for fabricating the vertical FET devices. For example, a semiconductor device comprises a lower source/drain region formed on a substrate, and first and second vertical semiconductor fins formed on the lower source/drain region. First and second metal gate electrodes are formed on sidewalls of the first and second vertical semiconductor fins, respectively. An upper source/drain region is formed on an upper surface of the first vertical semiconductor fin, and a vertical source/drain contact is formed in contact with the upper source/drain region formed on the first vertical semiconductor fin. An upper end of the second vertical semiconductor fin is encapsulated in an insulating material so that the upper end of the second vertical semiconductor fin is floating.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
forming a lower source/drain region on a semiconductor substrate;
forming a plurality of vertical semiconductor fins on the lower source/drain region, the plurality of vertical semiconductor fins comprising a first vertical semiconductor fin and a second vertical semiconductor fin;
forming a first metal gate electrode on a sidewall surface of the first vertical semiconductor fin, and a second metal gate electrode on a sidewall surface of the second vertical semiconductor fin;
forming an insulating layer to insulate the first and second metal gate electrodes;
forming an upper source/drain region on an upper surface of the first vertical semiconductor fin;
forming a vertical source/drain contact to the upper source/drain region formed on the upper surface of the first vertical semiconductor fin; and
encapsulating an upper end of the second vertical semiconductor fin in an insulating material so that the upper end of the second vertical semiconductor fin is floating.

2. The method of claim 1 , wherein the first vertical semiconductor fin, the first metal gate electrode, the lower source/drain region, and the upper source/drain region comprise a vertical FET (field effect transistor) device, and wherein the second vertical semiconductor fin, the second metal gate electrode, and the lower source/drain region comprise a vertical antifuse device.

3. The method of claim 2 , wherein the vertical FET device and the vertical antifuse device comprise a 2T memory cell of an OTP (one time programmable) memory array.

4. The method of claim 1 , wherein forming the plurality of vertical semiconductor fins on the lower source/drain region comprises:
epitaxially growing a layer of semiconductor material on the lower source/drain region; and
patterning the layer of semiconductor material to form the plurality of vertical semiconductor fins.

5. The method of claim 1 , wherein forming the first metal gate electrode on the sidewall surface of the first vertical semiconductor fin, and forming the second metal gate electrode on the sidewall surface of the second vertical semiconductor fin comprises:
forming a first high-k metal gate stack structure on the sidewall surface of the first vertical semiconductor fin;
forming a second high-k metal gate stack structure on the sidewall surface of the second vertical semiconductor fin;
depositing and patterning a layer of metallic material to form a first gate electrode layer on the first high-k metal gate stack structure and a second gate electrode layer on the second high-k metal gate stack structure.

6. The method of claim 5 , wherein the first and second high-k metal gate stack structures have a same thickness.

7. The method of claim 5 , wherein the second high-k metal gate stack structure is thinner than the first high-k metal gate stack structure.

8. The method of claim 1 , further comprising forming a common vertical gate contact to the first and second metal gate electrodes.

9. The method of claim 1 , further comprising:
forming a first vertical gate contact to the first metal gate electrode; and
forming a second vertical gate contact to the second metal gate electrode.

10. The method of claim 1 , further comprising:
forming an upper source/drain region on an upper surface of the second vertical semiconductor fin;
wherein encapsulating an upper end of the second vertical semiconductor fin in an insulating material comprises encapsulating the upper source/drain region on the upper surface of the second vertical semiconductor fin in the insulating material so that the upper source/drain region of the second vertical semiconductor fin is floating.

11. A semiconductor device, comprising:
a lower source/drain region formed on a semiconductor substrate;
a plurality of vertical semiconductor fins formed on the lower source/drain region, the plurality of vertical semiconductor fins comprising a first vertical semiconductor fin and a second vertical semiconductor fin;
a first metal gate electrode formed on a sidewall surface of the first vertical semiconductor fin, and a second metal gate electrode formed on a sidewall surface of the second vertical semiconductor fin;
an insulating layer to insulate the first and second metal gate electrodes;
an upper source/drain region formed on an upper surface of the first vertical semiconductor fin; and
a vertical source/drain contact formed in contact with the upper source/drain region formed on the upper surface of the first vertical semiconductor fin;
wherein an upper end of the second vertical semiconductor fin is encapsulated in an insulating material so that the upper end of the second vertical semiconductor fin is floating.

12. The semiconductor device of claim 11 , wherein the first vertical semiconductor fin, the first metal gate electrode, the lower source/drain region, and the upper source/drain region comprise a vertical FET (field effect transistor) device, and wherein, the second vertical semiconductor fin, the second metal gate electrode, and the lower source/drain region comprise a vertical antifuse device.

13. The semiconductor device of claim 12 , wherein the vertical FET device and the vertical antifuse device comprise a 2T memory cell, of an OTP (one time programmable) memory array.

14. The semiconductor device of claim 11 , wherein the plurality of vertical semiconductor fins on the lower source/drain region comprise epitaxial semiconductor material, that is epitaxially grown on the lower source/drain region.

15. The semiconductor device of claim 11 , wherein the first metal gate electrode comprises:
a first high-k metal gate stack structure formed on the sidewall surface of the first vertical semiconductor fin; and
a first gate electrode layer formed on the first high-k metal gate stack structure; and

wherein the second metal gate electrode comprises:
a second high-k metal gate stack structure formed on the sidewall surface of the second vertical semiconductor fin; and
a second gate electrode layer formed on the second high-k metal gate stack structure.

16. The semiconductor device of claim 15 , wherein the first and second high-k metal gate stack structures have a same thickness.

17. The semiconductor device of claim 15 , wherein the second high-k metal gate stack structure is thinner than the first high-k metal gate stack structure.

18. The semiconductor device of claim 11 , further comprising a common vertical gate contact formed in contact with the first and second metal gate electrodes.

19. The semiconductor device of claim 11 , further comprising:
a first vertical gate contact formed in contact with first metal gate electrode; and
a second vertical gate contact formed in contact with the second metal gate electrode.

20. The semiconductor device of claim 11 , further comprising:
an upper source/drain region formed on an upper surface of the second vertical semiconductor fin;
wherein the upper source/drain region on the upper surface of the second vertical semiconductor fin is encapsulated in the insulating material so that the upper source/drain region of the second vertical semiconductor fin is floating.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Li Juntao
• Wang Geng
• Zhang Qintao

Classifications

• H10W20/491 Primary

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• H10D84/8312

  the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions · CPC title

• H10D84/837

  comprising vertical IGFETs · CPC title

• H01L21/823418

  Electricity · mapped topic

• H01L27/088

  Electricity · mapped topic