Reconfigurable amplifier

Patent metadata

Field	Value
Publication number	US-12308875-B2
Application number	US-202418667309-A
Country	US
Kind code	B2
Filing date	May 17, 2024
Priority date	Aug 17, 2021
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

An amplifying circuit includes a first reconfigurable amplifier configured to selectively operate in a cascode mode or a non-cascode mode, wherein an input of the first reconfigurable amplifier is coupled to a first input of the amplifying circuit, and an output of the first reconfigurable amplifier is coupled to an output of the amplifying circuit. The amplifying circuit also includes a second reconfigurable amplifier configured to selectively operate in the cascode mode or the non-cascode mode, wherein an input of the second reconfigurable amplifier is coupled to a second input of the amplifying circuit, and an output of the second reconfigurable amplifier is coupled to the output of the amplifying circuit.

First claim

What is claimed is:

1. An apparatus, comprising:
a first receive path including a first reconfigurable amplifier configured to selectively operate in a cascode mode or a non-cascode mode, the first receive path having an input configured to receive a first intermediate frequency (IF) signal corresponding to a first radio frequency (RF) signal and a second IF signal corresponding to a second RF signal either simultaneously or individually;
a second receive path including a second reconfigurable amplifier configured to selectively operate in the cascode mode or the non-cascode mode, the second receive path having an input configured to receive a third IF signal corresponding to the first RF signal and a fourth IF signal corresponding to the second RF signal either simultaneously or individually, wherein the first receive path and the second receive path have a common output;
a first mixer coupled to the common output, wherein the first mixer is configured to frequency down-convert the first IF signal and the third IF signal; and
a second mixer coupled to the common output, wherein the second mixer is configured to frequency down-convert the second IF signal and the fourth IF signal.

2. The apparatus of claim 1 , further comprising a controller configured to cause both the first reconfigurable amplifier and the second reconfigurable amplifier to operate in the cascode mode in a carrier aggregation (CA) mode.

3. The apparatus of claim 2 , wherein the second reconfigurable amplifier is active when the first reconfigurable amplifier simultaneously receives the first IF signal and the second IF signal in the CA mode.

4. The apparatus of claim 3 , wherein the first reconfigurable amplifier is active when the second reconfigurable amplifier simultaneously receives the third IF signal and the fourth IF signal in the CA mode.

5. The apparatus of claim 2 , wherein the controller is configured to cause the first reconfigurable amplifier to operate in the non-cascode mode and turn off the second reconfigurable amplifier in a first multiplexing mode.

6. The apparatus of claim 5 , wherein the controller is configured to cause the second reconfigurable amplifier to operate in the non-cascode mode and turn off the first reconfigurable amplifier in a second multiplexing mode.

7. The apparatus of claim 1 , wherein the first reconfigurable amplifier comprises:
a first transistor having a gate coupled to the input of the first receive path, and a source coupled to a ground;
a second transistor having a source coupled to a drain of the first transistor, and a drain coupled to the common output;
a first load coupled to the common output; and
a first gate control circuit coupled to a gate of the second transistor, wherein the first gate control circuit is configured to:
in the cascode mode, bias the second transistor in a saturation region; and
in the non-cascode mode, bias the second transistor in a triode region.

8. The apparatus of claim 7 , wherein the first reconfigurable amplifier further comprises:
a supply control circuit, wherein the first load is coupled between the common output and the supply control circuit, and wherein the supply control circuit is configured to:
output a first supply voltage to the first load in the cascode mode; and
output a second supply voltage to the first load in the non-cascode mode,

wherein the first supply voltage is higher than the second supply voltage.

9. The apparatus of claim 7 , wherein the second reconfigurable amplifier comprises:
a third transistor having a gate coupled to the input of the second receive path, and a source coupled to the ground;
a fourth transistor having a source coupled to a drain of the third transistor, and a drain coupled to the common output;
a second load coupled to the common output; and
a second gate control circuit coupled to a gate of the fourth transistor, wherein the second gate control circuit is configured to:
in the cascode mode, bias the fourth transistor in the saturation region; and
in the non-cascode mode, bias the fourth transistor in the triode region.

10. The apparatus of claim 1 , further comprising:
a first module coupled to the input of the first receive path, the first module comprising:
first antennas; and
a first processing circuit configured to receive the first RF signal and the second RF signal via the first antennas, convert the first RF signal into the first IF signal, and convert the second RF signal into the second IF signal.

11. The apparatus of claim 10 , further comprising:
a second module coupled to the input of the second receive path, the second module comprising:
second antennas; and
a second processing circuit configured to receive the first RF signal and the second RF signal via the second antennas, convert the first RF signal into the third IF signal, and convert the second RF signal into the fourth IF signal.

Assignees

• Qualcomm Inc

Inventors

• Sankaranarayanan Janakiram
• Tan Jun
• Leung Lai Kan
• Gathman Timothy Donald
• Ipek Mehmet
• Choksi Ojas

Classifications

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F2200/294

  the amplifier being a low noise amplifier [LNA] · CPC title

• H03F3/19

  with semiconductor devices only · CPC title

• H03F2203/7227

  the gated amplifier being switched on or off by a switch in the supply circuit of the amplifier · CPC title

• H03F2203/30117

  the push circuit of the SEPP amplifier being a cascode circuit · CPC title