Reconfigurable amplifier

Patent metadata

Field	Value
Publication number	US-11683062-B2
Application number	US-202117404948-A
Country	US
Kind code	B2
Filing date	Aug 17, 2021
Priority date	Aug 17, 2021
Publication date	Jun 20, 2023
Grant date	Jun 20, 2023

Abstract

A reconfigurable amplifier includes a first transistor having a gate coupled to an input of the reconfigurable amplifier, and a source coupled to a ground. The reconfigurable amplifier also includes a gate control circuit, and a second transistor having a gate coupled to the gate control circuit, a source coupled to a drain of the first transistor, and a drain coupled to an output of the reconfigurable amplifier, wherein the gate control circuit is configured to output a bias voltage to the gate of the second transistor in a cascode mode, and output a switch voltage to the gate of the second transistor in a non-cascode mode. The reconfigurable amplifier further includes a load coupled to the output of the reconfigurable amplifier.

First claim

What is claimed is:

1. An apparatus, comprising:
a reconfigurable amplifier, comprising:
a first transistor having a gate coupled to an input of the reconfigurable amplifier, and a source coupled to a ground;
a second transistor having a source coupled to a drain of the first transistor, and a drain coupled to an output of the reconfigurable amplifier;
a gate control circuit coupled to a gate of the second transistor, wherein the gate control circuit is configured to:
output a first voltage to the gate of the second transistor in a first mode,

wherein the first voltage biases the second transistor in a saturation region; and
output a second voltage to the gate of the second transistor in a second

mode, wherein the second voltage biases the second transistor in a triode region;
a supply control circuit; and
a load coupled between the supply control circuit and the output of the reconfigurable amplifier;
wherein the supply control circuit is configured to:
output a first supply voltage to the load in the first mode; and
output a second supply voltage to the load in the second mode;
wherein the first supply voltage is higher than the second supply voltage.

2. The apparatus of claim 1 , wherein the second voltage is approximately equal to the second supply voltage.

3. The apparatus of claim 1 , further comprising:
an antenna coupled to the input of the reconfigurable amplifier; and
a mixer coupled to the output of the reconfigurable amplifier.

4. An apparatus, comprising:
a reconfigurable amplifier, comprising:
a first transistor having a gate coupled to an input of the reconfigurable amplifier, and a source coupled to a ground;
a second transistor having a source coupled to a drain of the first transistor, and a drain coupled to an output of the reconfigurable amplifier;
a load coupled to the output of the reconfigurable amplifier;
a bias circuit configured to output a first voltage;
a gate control circuit coupled to a gate of the second transistor, wherein the gate control circuit comprises:
a resistor;
a first switch coupled between the resistor and the bias circuit, wherein the resistor is coupled between the first switch and the gate of the second transistor; and
a second switch coupled between the resistor and a second voltage, wherein the resistor is coupled between the second switch and the gate of the second transistor.

5. The apparatus of claim 4 , wherein:
the first voltage biases the second transistor in a saturation region; and
the second voltage biases the second transistor in a triode region.

6. The apparatus of claim 4 , further comprising a controller configured to:
turn on the first switch and turn off the second switch in a first mode; and
turn off the first switch and turn on the second switch in a second mode.

7. The apparatus of claim 4 , wherein the gate control circuit further comprises:
a third switch; and
a capacitor, wherein the third switch is coupled between the capacitor and the ground, and the capacitor is coupled between the third switch and the gate of the second transistor.

8. The apparatus of claim 7 , further comprising a controller configured to:
turn on the first switch, turn off the second switch, and turn on the third switch in a first mode; and
turn off the first switch, turn on the second switch, and turn off the third switch in a second mode.

9. The apparatus of claim 8 , further comprising:
a fourth switch coupled between a first supply rail and the load; and
a fifth switch coupled between a second supply rail and the load;
wherein the controller is configured to turn on the fourth switch and turn off the fifth switch in the first mode, and turn off the fourth switch and turn on the fifth switch in the second mode.

10. An apparatus, comprising:
a reconfigurable amplifier, comprising:
a first transistor having a gate coupled to an input of the reconfigurable amplifier,

and a source coupled to a ground;
a second transistor having a source coupled to a drain of the first transistor, and a

drain coupled to an output of the reconfigurable amplifier;
a third transistor having a gate coupled to the input of the reconfigurable amplifier;

a fourth transistor having a source coupled to a drain of the third transistor, and a drain coupled to the output of the reconfigurable amplifier; and
a gate control circuit coupled to a gate of the second transistor and a gate of the fourth transistor, wherein the gate control circuit is configured to:
output a first voltage to the gate of the second transistor in a first mode,

wherein the first voltage biases the second transistor in a saturation region; and
output a second voltage to the gate of the second transistor in a second

mode, wherein the second voltage biases the second transistor in a triode region.

11. The apparatus of claim 10 , wherein:
each of the first transistor and the second transistor comprises a respective n-type field effect transistor; and
each of the third transistor and the fourth transistor comprises a respective p-type field effect transistor.

12. The apparatus of claim 10 , wherein the gate control circuit is configured to output a third voltage to the gate of the fourth transistor in the first mode, the third voltage biasing the fourth transistor in the saturation region.

13. The apparatus of claim 12 , wherein the gate control circuit is configured to couple the gate of the fourth transistor to the ground in the second mode.

14. The apparatus of claim 12 , further comprising a supply control circuit, wherein a source of the third transistor is coupled to the supply control circuit, and the supply control circuit is configured to:
output a first supply voltage to the source of the third transistor in the first mode; and
output a second supply voltage to the source of the third transistor in the second mode;
wherein the first supply voltage is higher than the second supply voltage.

15. The apparatus of claim 14 , wherein the second voltage is approximately equal to the second supply voltage.

Assignees

• Qualcomm Inc

Inventors

• Sankaranarayanan Janakiram
• Tan Jun
• Leung Lai Kan
• Gathman Timothy Donald
• Ipek Mehmet
• Choksi Ojas

Classifications

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F3/19

  with semiconductor devices only · CPC title

• H03F2200/294

  the amplifier being a low noise amplifier [LNA] · CPC title

• H04B1/18 Primary

  Input circuits, e.g. for coupling to an antenna or a transmission line (coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H) · CPC title

• H03F2203/7227

  the gated amplifier being switched on or off by a switch in the supply circuit of the amplifier · CPC title