Optimized Multi Gain LNA Enabling Low Current and High Linearity Including Highly Linear Active Bypass

Patent metadata

Field	Value
Publication number	US-2020328724-A1
Application number	US-202016860739-A
Country	US
Kind code	A1
Filing date	Apr 28, 2020
Priority date	Apr 4, 2017
Publication date	Oct 15, 2020
Grant date	—

Abstract

An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

First claim

1 . A low noise amplifier (LNA) comprising:
(a) a plurality of parallel-coupled cascode amplifiers, each having an input, an output, a bias port, and a source terminal and configured to receive an input signal on the input and generate an output signal having a selectable gain on the output; (b) a first inductance coupled to the output of each of the plurality of parallel-coupled cascode amplifiers and configured to be coupled to a power supply; and (c) a second inductance coupled to the source terminal of each of the plurality of parallel-coupled cascode amplifiers and configured to be coupled to ground; wherein the bias port of at least one of the plurality of parallel-coupled cascode amplifiers is selectively couplable to one of a bias voltage source or to ground.

2 . The invention of claim 1 , wherein at least a first cascode amplifier and a second cascode amplifier of the plurality of parallel-coupled cascode amplifiers are of significantly different current carrying sizes.

3 . The invention of claim 1 , wherein the selectable gain on the outputs of the plurality of parallel-coupled cascode amplifiers is set to a lower gain mode or to a higher gain mode as a function of the number of bias ports of the cascode amplifiers coupled to ground versus coupled to the power supply.

4 . The invention of claim 1 , wherein the second inductance has a selectable value.

5 . The invention of claim 4 , wherein the selectable value of the second inductance is a function of the selectable gain.

6 . The invention of claim 1 , wherein the bias ports of at least two cascode amplifiers of the plurality of parallel-coupled cascode amplifiers are selectively couplable to separate respective bias voltage sources.

7 . The invention of claim 1 , further including one or more source switches each coupled between the source terminals of respective pairs of the plurality of parallel-coupled cascode amplifiers.

8 . The invention of claim 7 , wherein an OPEN or CLOSED state of each source switch is a function of the selectable gain.

9 . The invention of claim 1 , further including a selectable resistance coupled in parallel with the first inductance.

10 . The invention of claim 9 , wherein selection of a state for the selectable resistance is a function of the selectable gain.

11 . The invention of claim 1 , further including a selectable capacitance coupled in parallel with the second inductance.

12 . The invention of claim 11 , wherein selection of a state for the selectable capacitance is a function of the selectable gain.

13 . A low noise amplifier (LNA) comprising:
(a) a plurality of parallel-coupled cascode amplifiers, each having an input, an output, a bias port, and a source terminal and configured to receive an input signal on the input and generate an output signal having a selectable gain on the output; (b) a plurality of degeneration inductances, each coupled to the source terminal of a corresponding one of the plurality of parallel-coupled cascode amplifiers and configured to be coupled to ground; and (c) one or more source switches each coupled between the source terminals of respective pairs of the plurality of parallel-coupled cascode amplifiers; wherein the bias port of at least one of the plurality of parallel-coupled cascode amplifiers is selectively couplable to one of a bias voltage source or to ground.

14 . The invention of claim 13 , wherein at least a first cascode amplifier and a second cascode amplifier of the plurality of parallel-coupled cascode amplifiers are of significantly different current carrying sizes.

15 . The invention of claim 13 , wherein the selectable gain on the outputs of the plurality of parallel-coupled cascode amplifiers is set to a lower gain mode or to a higher gain mode as a function of the number of bias ports of the cascode amplifiers coupled to ground versus coupled to the power supply.

16 . The invention of claim 13 , wherein the at least one of the plurality of degeneration inductances has a selectable value.

17 . The invention of claim 16 , wherein the selectable value of the at least one of the plurality of degeneration inductances is a function of the selectable gain.

18 . The invention of claim 13 , wherein the bias ports of at least two cascode amplifiers of the plurality of parallel-coupled cascode amplifiers are selectively couplable to separate respective bias voltage sources.

19 . The invention of claim 13 , wherein an OPEN or CLOSED state of each source switch is a function of the selectable gain.

20 . The invention of claim 13 , further including a selectable capacitance coupled in parallel with a corresponding one of the at least one of the plurality of degeneration inductances.

21 . The invention of claim 20 , wherein selection of a state for the selectable capacitance is a function of the selectable gain.

22 . The invention of claim 13 , further including a load inductance coupled to the output of each of the plurality of parallel-coupled cascode amplifiers and configured to be coupled to a power supply.

23 . The invention of claim 22 , further including a selectable resistance coupled in parallel with the load inductance.

24 . The invention of claim 23 , wherein selection of a state for the selectable resistance is a function of the selectable gain.

25 . A low noise amplifier (LNA) comprising:
(a) a plurality of parallel-coupled cascode amplifiers, each having an input, an output, a bias port, and a source terminal and configured to receive an input signal on the input and generate an output signal having a selectable gain on the output; (b) one or more source switches each coupled between the source terminals of respective pairs of the plurality of parallel-coupled cascode amplifiers; (c) a plurality of degeneration inductances, each coupled to the source terminal of a corresponding one of the plurality of parallel-coupled cascode amplifiers and configured to be coupled to ground; and (d) a load inductance coupled to the output of each of the plurality of parallel-coupled cascode amplifiers and configured to be coupled to a power supply; wherein the bias port of at least one of the plurality of parallel-coupled cascode amplifiers is selectively couplable to one of a bias voltage source or to ground; and wherein the selectable gain on the outputs of the plurality of parallel-coupled cascode amplifiers is set to a lower gain mode or to a higher gain mode as a function of the number of bias ports of the cascode amplifiers coupled to ground versus coupled to the power supply.

Assignees

• Psemi Corp

Inventors

• Ayranci Emre
• Sanner Miles

Classifications

• H03F3/193 Primary

  with field-effect devices (H03F3/195 takes precedence) · CPC title

• H03G2201/504

  by summing selected parallel amplifying paths, i.e. more amplifying/attenuating paths summed together · CPC title

• H03G3/001

  Digital control of analog signals · CPC title

• H03F2200/294

  the amplifier being a low noise amplifier [LNA] · CPC title

• H03G1/0029

  using field-effect transistors [FET] · CPC title