Receiver front end architecture for intra band carrier aggregation

Patent metadata

Field	Value
Publication number	US-2016142231-A1
Application number	US-201414540900-A
Country	US
Kind code	A1
Filing date	Nov 13, 2014
Priority date	Nov 13, 2014
Publication date	May 19, 2016
Grant date	—

Abstract

A receiver front end architecture for intra band carrier aggregation is disclosed. In an exemplary embodiment, an apparatus includes a first transistor having a gate terminal to receive an input signal, drain terminal to output an amplified signal, and a source terminal connected to a signal ground by a source degeneration inductor. The apparatus also includes a second transistor having a source terminal connected to the drain terminal of the first transistor and a drain terminal connected to a first load. The apparatus also includes a third transistor having a gate terminal connected to the drain terminal of the first transistor, a drain terminal connected to a second load and a source terminal connected to a signal ground.

First claim

What is claimed is:

1 . An apparatus comprising:
a first transistor having a gate terminal configured to receive an input signal, a drain terminal configured to output an amplified signal, and a source terminal connected to a signal ground by a source degeneration inductor; a second transistor having a source terminal connected to the drain terminal of the first transistor and a drain terminal connected to a first load; and a third transistor having a gate terminal connected to the drain terminal of the first transistor, a drain terminal connected to a second load and a source terminal connected to a signal ground.

2 . The apparatus of claim 1 , further comprising a fourth transistor having a source terminal connected to the drain terminal of the first transistor and a drain terminal connected to the first load, the fourth transistor configured to conduct an amount of current that is identical to or different from the second transistor.

3 . The apparatus of claim 2 , the fourth transistor selectively enabled or biased for DC coupling by a control signal to control current to the first load.

4 . The apparatus of claim 1 , further comprising one or more additional transistors having one or more gate terminals, respectively, connected to the drain terminal of the first transistor, one or more drain terminals connected to one or more loads, respectively, and one or more source terminals connected to the signal ground.

5 . The apparatus of claim 4 , the one or more drain terminals selectively connected to the one or more loads through one or more switches.

6 . The apparatus of claim 5 , the one or more switches selectively enabled by one or more control signals.

7 . The apparatus of claim 4 , the drain terminals of the one or more additional transistors selectively connected to the first load through one or more switches.

8 . The apparatus of claim 7 , the one or more switches selectively enabled by one or more control signals.

9 . The apparatus of claim 1 , the second transistor being selectively enabled or biased for DC coupling by a control signal.

10 . The apparatus of claim 1 , the drain terminal of the third transistor selectively connected to the second load through a switch.

11 . The apparatus of claim 10 , the switch selectively enabled or biased for DC coupling by a control signal.

12 . The apparatus of claim 1 , the drain terminal of the third transistor selectively connected to the first load through a switch.

13 . The apparatus of claim 12 , the switch selectively enabled by a control signal.

14 . The apparatus of claim 1 , further comprising a controller to generate control signals to selectively enable the second and third transistors or to bias the second and third transistors for DC coupling.

15 . The apparatus of claim 1 , the apparatus configured to perform configurable amplification and routing of carrier aggregation signals in a receiver.

16 . The apparatus of claim 1 , the apparatus formed on an integrated circuit.

17 . An apparatus comprising:
means for generating control signals that control how a signal is amplified and routed to one or more loads, the signal output from a first transistor having a source terminal connected to a signal ground by a source degeneration inductor; means for selectively connecting the signal to a first load through a first signal path based on the control signals; and means for selectively connecting the signal to a second load based on the control signals, said means including a transistor that receives the signal and has a source terminal connected to the signal ground.

18 . The apparatus of claim 17 , further comprising means for selectively connecting the signal to the first load through a second signal path based on the control signals, the second path configured to conduct an amount of current that is identical to or different from the first signal path.

19 . The apparatus of claim 17 , further comprising means for selectively connecting the signal to one or more additional loads through one or more additional signal paths based on the control signals, said means including one or more additional transistors connected to receive the signal and having one or more additional source terminals connected to the signal ground.

20 . The apparatus of claim 19 , further comprising means for selectively connect the one or more additional signal paths to the first signal path based on the control signals.

Assignees

• Qualcomm Inc

Inventors

• Rajendran Gireesh
• Sahota Gurkanwal Singh
• Kumar Rakesh

Classifications

• H03F3/68

  Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics {(power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602)} · CPC title

• H03F2200/492

  A coil being added in the source circuit of a transistor amplifier stage as degenerating element · CPC title

• H03F3/72

  Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal · CPC title

• H03F2200/294

  the amplifier being a low noise amplifier [LNA] · CPC title

• H03F1/26

  Modifications of amplifiers to reduce influence of noise generated by amplifying elements · CPC title