Three-dimensional memory and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12302558-B2
Application number	US-202117559181-A
Country	US
Kind code	B2
Filing date	Dec 22, 2021
Priority date	Sep 29, 2020
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

A three-dimensional memory includes a stack structure, a dummy structure and a gate line slit. The stack structure includes gate line layers and isolation layers stacked alternatively in the vertical direction. The dummy structure includes a first dummy section and a second dummy section. The gate line slit has one end extending into a gap formed by at least one of the first dummy section or the second dummy section. At least one of the first dummy section and the second dummy section partially overlaps a projection of the gate line slit onto the horizontal plane to realize connection between the dummy structure and the gate line slit.

First claim

What is claimed is:

1. A three-dimensional memory, comprising:
a stack structure comprising gate line layers and dielectric layers stacked alternatively in a vertical direction;
a dummy structure penetrating through the stack structure in the vertical direction and comprising a first dummy section and a second dummy section; and
a gate line slit penetrating through the stack structure in the vertical direction, wherein the gate line slit has one end extending into at least one gap formed by at least one of the first dummy section or the second dummy section, and the one end is in contact with a portion of the stack structure located in the at least one gap.

2. The three-dimensional memory of claim 1 , wherein
at least one of the first dummy section and the second dummy section partially over laps a projection of the gate line slit onto a horizontal plane, and
in a direction perpendicular to a direction in which the gate line slit extends, the overlapping part of the dummy structure and the projection of the gate line slit onto the horizontal plane has a width of M, and the gate line slit has a width of N, where M<0.1N.

3. The three-dimensional memory of claim 1 , wherein
the first dummy section and the second dummy section are disposed independently, and
the at least one gap is between the first dummy section and the second dummy section.

4. The three-dimensional memory of claim 3 , wherein the first dummy section and the second dummy section are disposed in parallel in a direction in which the gate line slit extends.

5. The three-dimensional memory of claim 1 , wherein
the at least one gap is located between the first dummy section and the second dummy section,
the dummy structure further comprises a third dummy section located in the at least one gap and connected with the first dummy section and the second dummy section, and
the third dummy section is spaced apart from the gate line slit by a preset distance.

6. The three-dimensional memory of claim 1 , wherein
the at least one gap comprises two gaps located respectively in a region enclosed by the first dummy section and a region enclosed by the second dummy section,
the dummy structure further comprises a third dummy section located between the first dummy section and the second dummy section and connected with the first dummy section and the second dummy section respectively, and
the third dummy section is spaced apart from the gate line slit by a preset distance.

7. The three-dimensional memory of claim 1 , wherein
the at least one gap is located between the first dummy section and the second dummy section,
the dummy structure further comprises a third dummy section connected with an end of the first dummy section away from the gate line slit and an end of the second dummy section away from the gate line slit, and
the third dummy section is spaced apart from the gate line slit by a preset distance.

8. The three-dimensional memory of claim 1 , wherein
the three-dimensional memory comprises a core region and a step region disposed sequentially in a second horizontal direction,
the gate line slit comprises a first gate line slit in the core region, and
the first gate line slit has an end facing the step region and connected with one of the dummy structure.

9. The three-dimensional memory of claim 1 , wherein
the three-dimensional memory comprises a plurality of blocks formed by dividing the stack structure by the gate line slit in a first horizontal direction,
the blocks comprise a first core region, a step region, and a second core region disposed sequentially in a second horizontal direction,
and the first horizontal direction is perpendicular to the second horizontal direction.

10. The three-dimensional memory of claim 9 , wherein
the plurality of blocks comprise adjacent first block and second block,
the gate line slit comprises a first gate line slit between the first block and the second block and in the first core region,
the gate line slit comprises a second gate line slit between the first block and the second block and in the second core region,
the first gate line slit has an end facing the step region and connected with one of the dummy structures, and
the second gate line slit has an end facing the step region and connected with one of the dummy structures.

11. The three-dimensional memory of claim 10 , wherein
the at least one gap is located between the first dummy section and the second dummy section,
the dummy structure further comprises a third dummy section connected with an end of the first dummy section away from the gate line slit and an end of the second dummy section away from the gate line slit, and
the third dummy section is spaced apart from the gate line slit by a preset distance.

12. The three-dimensional memory of claim 10 , wherein
the gate line slit comprises a plurality of third gate line slits spaced apart from each other on a side of the first block away from the second block and a plurality of fourth gate line slits spaced apart from each other on a side of the second block away from the first block,
the third gate line slits and the fourth gate line slits are located in the step region,
adjacent two of the third gate line slits are connected by the dummy structure, and
adjacent two of the fourth gate line slits are connected by the dummy structure.

13. The three-dimensional memory of claim 1 , wherein the dummy structure comprises an insulating material.

14. The three-dimensional memory of claim 1 , wherein a bottom surface of the dummy structure is lower than a bottom surface of the gate line slit.

15. The three-dimensional memory of claim 1 , further comprising a polysilicon layer on which the stack structure is disposed, wherein a bottom of the gate line slit extends at least to a surface of the polysilicon layer.

16. A method of manufacturing a three-dimensional memory, comprising:
forming a stack structure on a substrate, the stack structure comprising gate line sacrificial layers and dielectric layers stacked alternatively in a vertical direction;
forming a dummy structure penetrating through the stack structure in the vertical direction and comprising a first dummy section and a second dummy section; and
forming a gate line slit penetrating through the stack structure in the vertical direction, wherein the gate line slit has one end extending into a gap formed by the first dummy section and/or the second dummy section, and the one end is in contact with a portion of stack structure located in the gap.

17. The method of claim 16 , wherein
at least one of the first dummy section and the second dummy section partially overlaps a projection of the gate line slit onto a horizontal plane, and
in a direction perpendicular to a direction in which the gate line slit extends, the overlapping part of the dummy structure and the projection of the gate line slit onto the horizontal plane has a width of M, and the gate line slit has a width of N, wherein M<0.1N.

18. The method of claim 16 , wherein
the first dummy section and the second dummy section are disposed independently, and
the gap is between the first dummy section and the second dummy section.

19. The method of claim 18 , wherein
the three-dimensional memory comprises a core region and a step region disposed sequentially in a second horizontal direction,
the gate line slit comprises a first gate line slit in the core region, and
the first gate line slit has an end facing the step region and connected with one of the dummy s

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zhang Zhong
• Han Yuhui
• Kong Cuicui
• Zhang Kun

Classifications

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/20

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B41/20

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title