Method of manufacturing a hybrid device

Patent metadata

Field	Value
Publication number	US-12300759-B2
Application number	US-202217573044-A
Country	US
Kind code	B2
Filing date	Jan 11, 2022
Priority date	Jan 26, 2021
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

A method of manufacturing a micro-light-emitting diode display includes processing a wafer to form a plurality of functional chips integral with the wafer. A plurality of wafer tiles is defined in the wafer, wherein each wafer tile is composed of a cluster of functional chips. The wafer tiles are singulated by wafer dicing. A plurality of separate wafer tiles is bonded to a semiconductor wafer by hybrid bonding. The functional chips are singulated together with chips of the semiconductor wafer by dicing the bonded-together wafer tiles and semiconductor wafer.

First claim

What is claimed is:

1. A method of manufacturing a hybrid device, the method comprising:
processing a wafer to form a plurality of functional chips integral with the wafer;
defining a plurality of wafer tiles in the wafer, wherein each wafer tile is composed of a cluster of functional chips;
singulating the wafer tiles by wafer dicing;
bonding a plurality of separate wafer tiles to a semiconductor wafer by hybrid bonding; and
singulating the functional chips together with chips of the semiconductor wafer by dicing the bonded-together wafer tiles and the semiconductor wafer.

2. The method of claim 1 , wherein each wafer tile has a polygonal shape.

3. The method of claim 1 , wherein a first lateral dimension of each wafer tile is in a range between 20 and 60 mm and a second lateral dimension of each wafer tile is in a range between 20 and 60 mm.

4. The method of claim 1 , wherein the number of separate wafer tiles bonded to the semiconductor wafer is between 10 and 50.

5. The method of claim 1 , wherein the semiconductor wafer includes integrated circuits for controlling each functional chip of the plurality of functional chips.

6. The method of claim 1 , wherein the wafer and the semiconductor wafer exhibit different thermomechanical properties.

7. The method of claim 1 , wherein the wafer comprises a III-V semiconductor layer.

8. The method of claim 1 , wherein the semiconductor wafer is a Si wafer.

9. The method of claim 1 , wherein the wafer is a micro-LED wafer and each functional chip of the plurality of functional chips contains a micro-LED array.

10. The method of claim 9 , wherein each wafer tile comprises a substrate, a first semiconductor layer of a first dopant type arranged over the substrate, and a second semiconductor layer of a second dopant type arranged over the first semiconductor layer, the method further comprising:
removing the substrates of each wafer tile after bonding the plurality of separate wafer tiles to the semiconductor wafer.

11. The method of claim 10 , further comprising:
thinning the wafer tiles at a surface available after removing the substrates of each wafer tile.

12. The method of claim 10 , further comprising:
forming a common front side electrode layer on a surface of each wafer tile available after removing the substrates of each wafer tile or after thinning.

13. The method of claim 9 , wherein each micro-LED array of a wafer tile has a common front side electrode layer electrically connected to all micro-LEDs of the micro-LED array, and wherein common front side electrode layers of different micro-LED arrays are disconnected from each other.

14. The method of claim 13 , wherein the common front side electrode layer of each micro-LED array is formed by metal deposition and/or transparent conducting oxide generation.

Assignees

• Infineon Technologies Ag

Inventors

• Singer Frank
• Hellmund Oliver
• Holland Brendan
• Sperl Matthias

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10H20/0133

  with a substrate not being Group III-V materials · CPC title

• H10H20/01

  Manufacture or treatment · CPC title