Display contrast

US9728692B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9728692-B2
Application numberUS-201615376501-A
CountryUS
Kind codeB2
Filing dateDec 12, 2016
Priority dateDec 20, 2011
Publication dateAug 8, 2017
Grant dateAug 8, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Display devices with improved display contrast and methods of manufacturing the display devices. Some embodiments include a method of manufacturing a light emitting diode (LED) array. The method includes forming two mesa areas on a substrate, where a trench is defined between the two mesa areas. A pixel and a N-bus formation is formed on each of the two mesa areas to create a first LED and a second LED separated by the trench between the two mesa areas. At least a portion of the trench is filled with a non-transparent or substantially non-transparent polymeric material that absorbs light emitted from the first and second LEDs.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of manufacturing a light emitting diode (LED) array comprising: forming a first mesa area and a second mesa area, wherein a trench is defined between the first and second mesa areas; forming a pixel and a N-bus formation on each of the first and second mesa areas to create a first LED at the first mesa area and a second LED at the second mesa area; and filling at least a portion of the trench with a non-transparent or substantially non-transparent polymeric material that absorbs light emitted from the first and second LEDs. 2. The method of claim 1 , wherein the polymeric material is one of: polymide, epoxy, or benozcyclobutene. 3. The method of claim 1 , wherein: forming the pixel and the N-bus formation on the first mesa area includes defining a first space between the pixel and the N-bus formation; and filling the at least a portion of the trench with the polymeric material includes filing the first space between the pixel and the N-bus formation to electrically isolate the pixel and the N-bus formation. 4. The method of claim 3 , further comprising: etching a second space within the polymeric material above the pixel of the first mesa area; and depositing a metal within the space. 5. The method of claim 4 , further comprising depositing a metal layer on top of the polymeric material and the metal within the second space to electrically connect pixels of the first and second mesa areas. 6. The method of claim 5 , wherein; the first and second mesa areas are of different heights; and the polymeric material provides a conformal layer for depositing the metal layer. 7. The method of claim 1 , wherein forming the first mesa area and the second mesa area includes performing dry etching on a semiconductor layer. 8. The method of claim 1 , further comprising curing the polymeric material subsequent to filling the at least a portion of the trench with the polymeric material. 9. The method of claim 1 , wherein the first and second mesa areas are formed on a semiconductor layer, and the polymeric material at the trench absorbs the light emitted from the first and second LEDs and propagated through the semiconductor layer. 10. The method of claim 1 , wherein filling the at least a portion of the trench with the polymeric material includes annealing the polymeric material in an oxygen atmosphere. 11. The method of claim 1 , wherein the first and second LEDs are micro-LEDs. 12. The method of claim 1 , wherein filling the at least a portion of the trench with the polymeric material includes forming a polymeric material layer over the first and second mesa areas. 13. A light emitting diode (LED) array, comprising: a first mesa area; a second mesa area, a trench defined between the first and second mesa areas; a pixel and N-bus formation on each of the first and second mesa areas to form a first LED at the first mesa area and a second LED at the second mesa area; and a non-transparent or substantially non-transparent polymeric material within the trench to absorb light emitted from the first and second LEDs. 14. The LED array of claim 13 , wherein the polymeric material is one of: polymide, epoxy, or benozcyclobutene. 15. The LED array of claim 13 , wherein the non-transparent or substantially non-transparent polymeric material fills a space between the pixel and the N-bus formation on the first mesa area to electrically isolate the pixel and the N-bus formation. 16. The LED array of claim 15 , wherein: the polymeric material defines a second space within the polymeric material above the pixel of the first mesa area; and the LED array further includes a metal deposited within the second space. 17. The LED array of claim 16 , further comprising a metal layer on top of the polymeric material and the metal within the second space to electrically connect the pixels of the first and second mesa areas. 18. The LED array of claim 17 , wherein: the first and second mesa areas are of different heights; and the polymeric material provides a conformal layer for the metal layer disposed on top of the polymeric material. 19. The LED array of claim 13 , wherein the first and second mesa areas are formed on a semiconductor layer, and the polymeric material at the trench absorbs the light emitted from the first and second LEDs and propagated through the semiconductor layer. 20. The LED array of claim 13 , wherein the first and second LEDs are micro-LEDs.

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What does patent US9728692B2 cover?
Display devices with improved display contrast and methods of manufacturing the display devices. Some embodiments include a method of manufacturing a light emitting diode (LED) array. The method includes forming two mesa areas on a substrate, where a trench is defined between the two mesa areas. A pixel and a N-bus formation is formed on each of the two mesa areas to create a first LED and a se…
Who is the assignee on this patent?
Oculus Vr Llc
What technology area does this patent fall under?
Primary CPC classification H01L33/58. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 08 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).