Semiconductor packages and methods for manufacturing thereof

Patent metadata

Field	Value
Publication number	US-12300559-B2
Application number	US-202117552914-A
Country	US
Kind code	B2
Filing date	Dec 16, 2021
Priority date	Dec 17, 2020
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

A package includes a dielectric carrier, an electronic component mounted on the dielectric carrier, and an encapsulant encapsulating at least part of the dielectric carrier and the electronic component. Corresponding methods of manufacturing the package are also described.

First claim

What is claimed is:

1. A package, comprising:
a dielectric carrier;
an electronic component mounted on the dielectric carrier;
an encapsulant encapsulating at least part of the dielectric carrier and the electronic component,
an electrically conductive layer exposed beyond the encapsulant, such that each sidewall and a bottom surface of the electrically conductive layer are uncovered by the encapsulant, and the electrically conductive layer is connected with the electronic component, and
at least one lead electrically coupled with the electronic component and extending beyond the encapsulant
wherein the dielectric carrier is an electrically insulating tape, and
wherein the electronic component is in direct contact with the electrically insulating tape.

2. The package of claim 1 , wherein the package is configured as a tie bar-less package.

3. The package of claim 1 , further comprising a metallization exposed at a sidewall of the encapsulant and being accessible for lead tip inspection.

4. The package of claim 1 , wherein a material of the dielectric carrier is thermally conductive.

5. The package of claim 1 , wherein the dielectric carrier is completely free of any metal or other electrically conductive structure.

6. The package of claim 1 , wherein the dielectric carrier consists of dielectric or electrically insulating material.

7. A package, comprising:
an electronic component;
an encapsulant encapsulating at least part of the electronic component;
an electrically conductive layer exposed beyond the encapsulant, such that each sidewall and a bottom surface of the electrically conductive layer are uncovered by the encapsulant, and the electrically conductive layer is connected with the electronic component; and
at least one lead electrically coupled with the electronic component and extending beyond the encapsulant.

8. The package of claim 7 , wherein the package is configured as a tie bar-less package.

9. The package of claim 7 , further comprising a metallization exposed at a sidewall of the encapsulant and being accessible for lead tip inspection.

10. The package of claim 7 , wherein the electrically conductive layer forms a carrier on which the electronic component is mounted, the package further comprising:
a plurality of leads extending along four sides around the carrier, being electrically coupled with the electronic component and extending beyond the encapsulant along all four sides.

11. The package of claim 10 , wherein the encapsulant comprises steps along at least two opposing ones of the four sides so that portions of the leads are exposed at a top surface, a bottom surface, and a lateral surface of each respective step.

12. The package of claim 11 , wherein sections of the leads and sections of the encapsulant at a respective step extend up to different vertical levels with respect to the leads at the top surface and/or at the bottom surface.

13. The package of claim 7 , wherein the electrically conductive layer partially covers the encapsulant.

14. A package, comprising:
an electronic component;
an encapsulant encapsulating at least part of the electronic component;
a plurality of leads electrically coupled with the electronic component and extending beyond two opposing sides of the encapsulant; and
a lead tip inspection metallization exposed beyond the encapsulant on at least one sidewall of the encapsulant,
wherein the lead tip inspection metallization is exposed beyond a first main side of the encapsulant and extends uninterrupted along a first plane coplanar with the first main side of the encapsulant onto a second plane coplanar with the at least one sidewall of the encapsulant, and
wherein the at least one sidewall is arranged at another side of the encapsulant than the two opposing sides at which the leads extend beyond the encapsulant.

15. The package of claim 14 , wherein the exposed lead tip inspection metallization forms part of a carrier on which the electronic component is mounted.

Assignees

• Infineon Technologies Ag

Inventors

• Yeo Si Hao Vincent
• Cha Chan Lam
• Cheong Ying Dieh
• Chiang Chau Fatt
• Danny Koh Cher Hau
• Daryl Wee Wern Ken
• Lee Swee Kat
• Loo Desmond Jenn Yong
• Lopez Fortunato
• Morban Norliza
• Saw Khay Chwan Andrew
• Tey Sock Chien
• Wang mei yong

Classifications

• H10W74/01

  Manufacture or treatment · CPC title

• H10W70/411

  Chip-supporting parts, e.g. die pads · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W70/479

  on or in insulating or insulated package substrates, interposers, or redistribution layers · CPC title