Gate stack treatment

Patent metadata

Field	Value
Publication number	US-12300549-B2
Application number	US-202318309416-A
Country	US
Kind code	B2
Filing date	Apr 28, 2023
Priority date	Sep 26, 2018
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

First claim

What is claimed is:

1. A method, comprising:
forming a fin on a substrate;
forming a dielectric layer on the fin;
exposing the dielectric layer to a fluorine-based gas; and
depositing, after exposing the dielectric layer to the fluorine-based gas, a work function metal on the dielectric layer.

2. The method of claim 1 , further comprising:
forming a sacrificial blocking layer on the dielectric layer; and
annealing the dielectric layer to drive the fluorine into the dielectric layer.

3. The method of claim 1 , wherein forming the dielectric layer comprises forming an interlayer dielectric layer and a high-k dielectric layer on the fin.

4. The method of claim 1 , wherein exposing the dielectric layer to the fluorine-based gas comprises performing a fluorination operation for a time between about 1 s and about 30 min.

5. The method of claim 1 , wherein exposing the dielectric layer to the fluorine-based gas comprises soaking the dielectric layer for a time of about 10 min and under an ambient pressure of about 70 Torr.

6. The method of claim 1 , wherein exposing the dielectric layer to the fluorine-based gas comprises removing a byproduct contamination in the dielectric layer.

7. The method of claim 1 , wherein exposing the dielectric layer to the fluorine-based gas comprises reducing a number of trap centers in the dielectric layer and at an interface between the dielectric layer and the fin.

8. A method, comprising:
forming a fin on a substrate;
forming a dielectric layer on the fin;
forming a barrier layer on the dielectric layer; and
forming, on the barrier layer, a work function layer doped with fluorine.

9. The method of claim 8 , wherein forming the work function layer comprises performing a fluorination process on the work function layer by soaking the work function layer in a fluorine-based gas for a time between about 1 s and about 30 min.

10. The method of claim 8 , wherein forming the work function layer comprises:
forming a plurality of work function sublayers; and
doping each of the plurality of work function sublayers with fluorine.

11. The method of claim 8 , wherein forming the work function layer comprises:
forming a plurality of work function sublayers; and
selectively doping one of the plurality of work function sublayers with fluorine.

12. The method of claim 8 , wherein forming the work function layer comprises exposing the work function layer to one or more of fluorine (F 2 ), nitrogen trifluoride (NF 3 ), fluoroform (CHF 3 ), tetrafluoromethane (CF 4 ), sulfur hexafluoride (SF 6 ), hexafluoroethane (C 2 F 6 ), and combinations thereof.

13. The method of claim 8 , wherein forming the barrier layer comprises doping the barrier layer with fluorine.

14. A method, comprising:
forming a dielectric layer on a first fin and a second fin;
selectively forming a first work function layer on a portion of the dielectric layer, wherein the portion of the dielectric layer is on the first fin;
forming a second work function layer on the first and second fins to form a first transistor on the first fin and a second transistor on the second fin; and
exposing the second work function layer to a fluorine-based gas.

15. The method of claim 14 , wherein exposing the second work function layer to the fluorine-based gas comprises tuning threshold voltages of the first and second transistors.

16. The method of claim 14 , wherein exposing the second work function layer to the fluorine-based gas comprises decreasing a threshold voltage of the second transistor.

17. The method of claim 14 , wherein selectively forming the first work function layer comprises masking an other portion of the dielectric layer, wherein the other portion of the dielectric layer is on the second fin.

18. The method of claim 14 , wherein forming the dielectric layer comprises exposing the dielectric layer to a fluorine-based gas.

19. The method of claim 14 , further comprising prior to forming the first work function layer, forming a fluorine-doped barrier layer on the dielectric layer.

20. The method of claim 14 , wherein forming the second work function layer comprises configuring a first threshold voltage of the first transistor and a second threshold voltage of the second transistor, wherein the first and second threshold voltages are different.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Savant Chandrashekhar Prakash
• Tsai Chia-Ming
• Chen Ming-Te
• Lin Shih-Chi
• Chong Zack
• Yu Tien-Wei

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10D64/01332

  Making the insulator · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10D64/0134

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title