Gate stack treatment

Patent metadata

Field	Value
Publication number	US-11088029-B2
Application number	US-201916376432-A
Country	US
Kind code	B2
Filing date	Apr 5, 2019
Priority date	Sep 26, 2018
Publication date	Aug 10, 2021
Grant date	Aug 10, 2021

Abstract

The present disclosure describes a method for forming gate stack layers with a fluorine concentration up to about 35 at. %. The method includes forming dielectric stack, barrier layer and soaking the dielectric stack and/or barrier layer in a fluorine-based gas. The method further includes depositing one or more work function layers on the high-k dielectric layer, and soaking at least one of the one or more work function layers in the fluorine-based gas. The method also includes optional fluorine drive in annealing process, together with sacrificial blocking layer to avoid fluorine out diffusion and loss into atmosphere.

First claim

What is claimed is:

1. A method comprising:
forming an interfacial dielectric on fins disposed on a substrate;
depositing a high-k dielectric layer on the interfacial dielectric;
depositing one or more work function layers on the high-k dielectric layer;
heating the substrate to a temperature between about 70° C. and about 950° C.; and
soaking at least one of the one or more work function layers in a fluorine-based gas to dope the at least one of the one or more work function layers while heating the substrate.

2. The method of claim 1 , wherein soaking the at least one of the one or more work function layers in the fluorine-based gas comprises soaking the at least one of the one or more work function layers in fluorine gas (F 2 ), nitrogen trifluoride (NF 3 ), fluoroform (CHF 3 ), tetrafluoromethane (CF 4 ), sulfur hexafluoride (SF 6 ), hexafluoroethane (C 2 F 6 ), or combinations thereof to incorporate fluorine in the at least one of the one or more work function layers.

3. The method of claim 1 , further comprising, prior to depositing the high-k dielectric layer, soaking the interfacial dielectric in the fluorine-based gas to dope the interfacial dielectric with fluorine while heating the substrate.

4. The method of claim 1 , wherein soaking the at least one of the one or more work function layers in the fluorine-based gas comprises soaking the at least one of the one or more work function layers at an ambient pressure between about 0.5 Torr and about 150 Torr.

5. The method of claim 1 , further comprising, prior to depositing the one or more work function layers:
depositing a barrier layer on the high-k dielectric layer;
soaking the barrier layer in the fluorine-based gas at a temperature between about 70° C. and about 950° C.;
depositing a sacrificial blocking layer on the barrier layer;
annealing the substrate at a temperature between about 70° C. and about 550° C.; and
removing the sacrificial blocking layer.

6. The method of claim 1 , wherein soaking the at least one or more work function layers comprises performing an implantation-free soaking process on the at least one or more work function layers.

7. The method of claim 1 , wherein soaking the at least one or more work function layers comprises performing a plasma-free soaking process on the at least one or more work function layers.

8. The method of claim 1 , further comprising:
depositing a sacrificial blocking layer over and in contact with the high-k dielectric layer;
annealing the substrate with the high-k dielectric layer being capped with the sacrificial blocking layer;
removing the sacrificial blocking layer;
depositing a capping layer over and in contact with the annealed high-k dielectric layer; and
depositing a barrier layer over the capping layer and under the one or more work function layers.

9. A method, comprising:
forming an interfacial dielectric over a fin structure of a substrate;
depositing a high-k dielectric layer over the interfacial dielectric;
depositing a first work function layer over the high-k dielectric layer;
doping the first work function layer with fluorine by soaking the first work function layer in a fluorine-based gas;
depositing a second work function layer over the soaked first work function layer; and
doping the second work function layer with fluorine by soaking the second work function layer in the fluorine-based gas.

10. The method of claim 9 , wherein doping the first work function layer comprises soaking the first work function layer with one of fluorine gas (F 2 ), nitrogen trifluoride (NF 3 ), fluoroform (CHF 3 ), tetrafluoromethane (CF 4 ), sulfur hexafluoride (SF 6 ), and hexafluoroethane (C 2 F 6 ) at a temperature between about 70° C. and about 950° C.

11. The method of claim 9 , wherein doping the first work function layer comprises exposing a surface of the first work function layer to the fluorine-based gas, and wherein depositing the second work function layer comprises depositing the second work function layer over and in contact with the surface of the first work function layer.

12. The method of claim 9 , further comprising:
depositing a capping layer over the high-k dielectric layer; and
depositing a barrier layer over the capping layer and under the first work function layer.

13. The method of claim 12 , further comprising:
doping the barrier layer with fluorine by soaking the barrier layer in the fluorine-based gas while heating the substrate;
depositing a sacrificial blocking layer over the barrier layer;
annealing the substrate at a temperature between about 70° C. and about 550° C. with the sacrificial layer being over the barrier layer; and
removing the sacrificial blocking layer.

14. The method of claim 9 , further comprising depositing an aluminum-contained gate metal layer over the second work function layer.

15. A method, comprising:
forming an interfacial dielectric over a substrate;
depositing a high-k dielectric layer over the interfacial dielectric;
depositing a first work function layer over the high-k dielectric layer;
soaking the first work function layer in a fluorine-based gas to dope the first work function layer with fluorine while heating the substrate;
depositing a second work function layer over the soaked first work function layer; and
depositing a gate metal layer over the second work function layer with the second work function layer being free from fluorine.

16. The method of claim 15 , wherein soaking the first work function layer comprises exposing the first work function layer to one of fluorine gas (F 2 ), nitrogen trifluoride (NF 3 ), fluoroform (CHF 3 ), tetrafluoromethane (CF 4 ), sulfur hexafluoride (SF 6 ), and hexafluoroethane (C 2 F 6 ).

17. The method of claim 15 , further comprising depositing a barrier layer over the high-k dielectric layer, and wherein depositing the first work function layer comprises depositing the first work function layer over a first portion of the barrier layer with a second portion of the barrier layer being exposed.

18. The method of claim 17 , wherein depositing the second work function layer comprises depositing the second work function layer over and in contact with the second portion of the barrier layer.

19. The method of claim 17 , further comprising depositing a capping layer over the high-k dielectric layer and under the barrier layer.

20. The method of claim 19 , further comprising:
depositing a sacrificial blocking layer over the barrier layer;
annealing the substrate at a temperature between about 70° C. and about 550° C.; and
removing the sacrificial blocking layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Savant Chandrashekhar Prakash
• Tsai Chia-Ming
• Chen Ming-Te
• Lin Shih-Chi
• Chong Zack
• Yu Tien-Wei

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10D64/01332

  Making the insulator · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10D64/0134

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title