FinFET doping methods and structures thereof

Patent metadata

Field	Value
Publication number	US-9960053-B2
Application number	US-201514970291-A
Country	US
Kind code	B2
Filing date	Dec 15, 2015
Priority date	Dec 15, 2015
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

A method and structure for providing conformal doping of FinFET fin structures, for example by way of a thermal treatment process, includes forming a gate stack at least partially over a fin extending from a substrate. In various embodiments, a barrier metal layer is deposited over the gate stack. By way of example, a thermal fluorine treatment is performed, where the thermal fluorine treatment forms a fluorinated layer within the barrier metal layer, and where the fluorinated layer includes a plurality of fluorine atoms. In some embodiments, after forming the fluorinated layer, an anneal is performed to drive at least some of the plurality of fluorine atoms into the gate stack (e.g., into the interfacial layer and the high-K dielectric layer), thereby conformally doping the gate stack with the at least some of the plurality of fluorine atoms.

First claim

What is claimed is:

1. A method of semiconductor device fabrication, comprising:
forming a gate stack at least partially over a fin extending from a substrate;
depositing a barrier metal layer over the gate stack;
performing a thermal fluorine treatment, wherein the thermal fluorine treatment forms a fluorinated layer within the barrier metal layer, and wherein the fluorinated layer includes a plurality of fluorine atoms; and
after forming the fluorinated layer, performing an anneal to drive at least some of the plurality of fluorine atoms into the gate stack, thereby doping the gate stack with the at least some of the plurality of fluorine atoms.

2. The method of claim 1 , further comprising:
after forming the fluorinated layer and prior to performing the anneal, forming a capping layer over the fluorinated layer.

3. The method of claim 2 , wherein forming the capping layer includes forming a chemical vapor deposition (CVD)-deposited silicon layer.

4. The method of claim 1 , wherein the anneal includes a rapid thermal anneal (RTA) process.

5. The method of claim 1 , wherein the gate stack includes an interfacial layer formed at least partially over the fin and a gate dielectric layer formed over the interfacial layer, and wherein the barrier metal layer is deposited over the gate dielectric layer.

6. The method of claim 1 , wherein the performing the anneal to drive at least some of the plurality of fluorine atoms into the gate stack conformally dopes the gate stack with the at least some of the plurality of fluorine atoms.

7. The method of claim 1 , wherein the depositing the barrier metal layer includes depositing a titanium silicon nitride (TiSiN) layer.

8. The method of claim 7 , wherein the fluorinated layer includes a fluorinated TiSiN layer.

9. The method of claim 1 , further comprising:
after depositing the barrier metal layer and prior to performing the thermal fluorine treatment, performing a post metallization anneal (PMA) process.

10. The method of claim 1 , wherein the performing the thermal fluorine treatment includes flowing fluorine (F 2 ) gas over the barrier metal layer at a temperature of about 250-300° C.

11. The method of claim 2 , further comprising:
removing the capping layer; and
forming a gate metal layer over the barrier metal layer.

12. A method, comprising:
forming an interfacial layer over a fin extending from a substrate and forming a gate dielectric layer over the interfacial layer;
depositing a barrier metal layer over the gate dielectric layer;
performing a thermal fluorine treatment process, wherein the thermal fluorine treatment process includes:
flowing a fluorine (F 2 ) gas over the barrier layer at a processing temperature substantially equal to a thermal fluorine treatment temperature; and
responsive to flowing the fluorine (F 2 ) gas over the barrier layer at the thermal fluorine treatment temperature, introducing a plurality of fluorine atoms into a first portion of the barrier metal layer to form a fluorinated barrier metal layer; and

performing a rapid thermal anneal (RTA) process to drive at least some of the plurality of fluorine atoms into the interfacial layer and the gate dielectric layer.

13. The method of claim 12 , further comprising:
after performing the thermal fluorine treatment process and prior to performing the RTA process, performing a capping layer deposition process including:
ramping the processing temperature from the thermal fluorine treatment temperature to a capping layer deposition temperature; and
depositing a capping layer over the fluorinated barrier metal layer at the capping layer deposition temperature.

14. The method of claim 13 , further comprising:
responsive to the depositing the capping layer at the capping layer deposition temperature, at least partially redistributing the plurality of fluorine atoms from the fluorinated barrier metal layer into both a second portion of the barrier metal layer and into the capping layer, thereby forming a fluorinated capping layer.

15. The method of claim 12 , wherein the performing the RTA process drives at least some of the plurality of fluorine atoms to one or more of a fin/interfacial layer interface, an interfacial layer/gate dielectric layer interface, and a gate dielectric layer/barrier metal layer interface.

16. The method of claim 14 , further comprising:
removing the fluorinated capping layer; and
forming a gate metal layer over the fluorinated barrier metal layer.

17. The method of claim 12 , wherein the at least some of the plurality of fluorine atoms passivate bulk and interfacial defects of each of the interfacial layer and the gate dielectric layer.

18. A method of fabricating a semiconductor device, comprising:
depositing a nitride-containing barrier layer over a high-K gate stack, the high-K gate stack disposed over a fin extending from a substrate;
flowing a fluorine gas over the semiconductor device at a temperature greater than room temperature, wherein the flowing the fluorine gas forms a conformal fluorinated layer within the nitride-containing barrier layer, and wherein the conformal fluorinated layer includes a plurality of fluorine atoms;
forming a capping layer over the conformal fluorinated layer;
after forming the capping layer, performing a rapid thermal anneal process to drive at least some of the plurality of fluorine atoms into the high-K gate stack and into an interfacial layer disposed below the high-K gate stack;
wherein the nitride-containing barrier layer prevents outgassing of the plurality of fluorine atoms during the rapid thermal anneal process.

19. The method of claim 18 , wherein the nitride-containing barrier layer includes titanium silicon nitride (TiSiN), titanium nitride (TiN), tantalum silicon nitride (TaSiN), or tantalum nitride (TaN).

20. The method of claim 18 , further comprising:
after performing the rapid thermal anneal process, removing the capping layer; and
forming a gate metal layer over the nitride-containing barrier layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hou Cheng-Hao
• Yu xiong-fei
• Hsu Chia-Wei

Classifications

• H10P32/30

  Diffusion for doping of conductive or resistive layers · CPC title

• H10P14/416

  of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10P14/412

  Deposition of metallic or metal-silicide materials · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D64/01338

  with a treatment, e.g. annealing, after the formation of the conductor · CPC title