Driving controller for displaying image using dithering patterns and display device having the same

Patent metadata

Field	Value
Publication number	US-12300144-B2
Application number	US-202117478759-A
Country	US
Kind code	B2
Filing date	Sep 17, 2021
Priority date	Oct 21, 2019
Publication date	May 13, 2025
Grant date	May 13, 2025

Abstract

A driving controller of a display device includes a driving frequency controller for receiving an image signal, determining a driving frequency based on the image signal, and outputting a masking enable signal corresponding to the driving frequency, and an image processor for converting the image signal into a data signal and outputting the data signal, wherein the image processor sequentially converts, based on the masking enable signal being at an active level, a part of bits of the image signal into the data signal corresponding to a plurality of dither patterns.

First claim

What is claimed is:

1. A driving controller comprising:
a driving frequency controller configured to receive an image signal, determine a driving frequency based on the image signal, and output a first signal; and
an image processor configured to receive an input synchronization signal and the image signal, and convert the image signal into a data signal and output the data signal,
wherein the image processor sequentially converts the image signal into the data signal corresponding to a plurality of dither patterns based on the first signal being at an active level, and
wherein a frequency of the first signal corresponds to the driving frequency when the driving frequency and a frequency of the input synchronization signal are different from each other.

2. The driving controller of claim 1 , wherein the image processor converts the image signal into the data signal in synchronization with the input synchronization signal based on the first signal being at the active level, and
wherein the image processor holds converting the image signal into the data signal based on the first signal being at an inactive level.

3. The driving controller of claim 2 , wherein the image processor output the data signal in synchronization with an output enable signal, and
wherein the output enable signal is maintained at the inactive level when the first signal is at the inactive level.

4. The driving controller of claim 1 , wherein the image processor selects the plurality of dither patterns of a predetermined order based on the first signal being at the active level, and converts a part of bits of the image signal into the data signal by using the plurality of dither patterns, and
wherein the image processor holds selection of the plurality of dither patterns based on the first signal being at an inactive level.

5. The driving controller of claim 1 , wherein the first signal has a first active period when the driving frequency has a first frequency,
wherein the first signal has a second active period when the driving frequency has a second frequency lower than the first frequency, and
wherein the second active period is shorter than the first active period.

6. The driving controller of claim 1 , wherein the first signal is maintained at the active level based on a frequency of an input synchronization signal matching the driving frequency.

7. The driving controller of claim 1 , wherein the image processor comprises:
a gamma correction part configured to correct a gradation level of the image signal in synchronization with the input synchronization signal and output the image signal having a corrected gradation level;
a dithering part configured to output image data by sequentially changing a part of bits of the image signal to the plurality of dither patterns; and
an output part configured to output the image data as the data signal in synchronization with an output synchronization signal.

8. The driving controller of claim 1 , wherein the image processor comprises:
a spot correction part configured to output image data by sequentially changing a part of bits of the image signal to a plurality of spot correction patterns in synchronization with an input synchronization signal; and
an output part configured to output the image data as the data signal in synchronization with an output synchronization signal.

9. The driving controller of claim 1 , wherein the driving frequency controller comprises:
a still image determination part configured to determine whether the image signal is a still image;
a flicker determination part configured to determine a flicker index of the image signal based on determination by the still image determination part that the image signal is the still image; and
a frequency determination part configured to determine the driving frequency based on the flicker index.

10. The driving controller of claim 9 , wherein the frequency determination part determines the driving frequency to be lower than the frequency of the input synchronization signal based on the image signal being the still image and the flicker index of the image signal being smaller than or equal to a predetermined value.

11. A display device comprising:
a display panel including a plurality of pixels respectively connected to a plurality of data lines and a plurality of scan lines;
a data driving circuit configured to drive the plurality of data lines;
a scan driving circuit configured to drive the plurality of scan lines; and
a driving controller configured to receive an input synchronization signal and an image signal, and control the data driving circuit and the scan driving circuit,
wherein the driving controller comprises:
a driving frequency controller configured to determine a driving frequency of the display panel based on the image signal and output a first signal; and
an image processor configured to receive the input synchronization signal and the image signal, and convert the image signal into a data signal and output the data signal,
wherein the image processor sequentially converts the image signal into the data signal corresponding to a plurality of dither patterns based on the first signal being at an active level, and
wherein a frequency of the first signal corresponds to the driving frequency when the driving frequency and a frequency of the input synchronization signal are different from each other.

12. The display device of claim 11 , wherein the image processor converts, in synchronization with the input synchronization signal based on the first signal being at the active level, a part of bits of the image signal into the data signal corresponding to the plurality of dither patterns of a predetermined order.

13. The display device of claim 11 , wherein the first signal has a first active period when the driving frequency has a first frequency,
wherein the first signal has a second active period when the driving frequency has a second frequency lower than the first frequency, and
wherein the second active period is shorter than the first active period.

14. The display device of claim 11 , wherein the first signal is maintained at the active level based on a frequency of an input synchronization signal matching the driving frequency.

15. The display device of claim 11 , wherein the display panel comprises a first display region and a second display region,
wherein the driving frequency controller determines a first driving frequency corresponding to the first display region and a second driving frequency corresponding to the second display region, and outputs the first signal corresponding to the first driving frequency and a second signal corresponding to the second driving frequency, and
wherein the image processor sequentially converts a first image signal corresponding to the first display region of the image signal into a first data signal corresponding to a first plurality of dither patterns in synchronization with the input synchronization signal based on the first signal being at the active level, sequentially converts a second image signal corresponding to the second display region of the image signal into a second data signal corresponding to a second plurality of dither patterns in synchronization with the input synchronization signal based on the second signal being at the active level, and outputs the first data signal and the second data signal as the data signal.

16. The display device of claim 15 , wherein the first driving frequency is the same as the frequency of the input synchronization signal, and the second driving frequency is lower than the freque

Assignees

• Samsung Display Co Ltd

Inventors

• Ahn Kuk-Hwan
• Kim Hongsoo
• Jung Junheyung
• Yoo Youngwook
• Lee Jungyu
• Lim Hyunjun
• Chun Byung Ki

Classifications

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G09G5/18

  Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12}) · CPC title

• G09G2340/0435

  Change or adaptation of the frame rate of the video stream · CPC title

• G09G3/2044 Primary

  using dithering · CPC title

• G09G3/2077

  by a combination of two or more gradation control methods · CPC title