Digital phase locked loop and operating method of digital phase locked loop

Patent metadata

Field	Value
Publication number	US-10158367-B1
Application number	US-201815861962-A
Country	US
Kind code	B1
Filing date	Jan 4, 2018
Priority date	Jun 21, 2017
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

A digital phase locked loop includes a digital phase detector, a digital loop filter, a digital controlled oscillator, a first divider that divides the second frequency of the oscillation signal depending on a first division value and outputs the division result as a division signal having a third frequency, a second divider that divides the second frequency of the oscillation signal depending on a second division value and outputs the division result as an output signal having a final frequency, a dithering block that receives the division signal and performs dithering on the first division value based on a preset pattern as cycles of the division signal pass, and a digital phase domain filter that performs second low pass filtering on the division signal in a phase domain and outputs the result of the second low pass filtering as the feedback signal.

First claim

What is claimed is:

1. A digital phase locked loop comprising:
a digital phase detector configured to output phase information based on a phase of a reference signal having a reference frequency and a phase of a feedback signal having a first frequency such that the phase information indicates whether the phase of the feedback signal is advanced or delayed with respect to the phase of the reference signal;
a digital loop filter configured to perform first low pass filtering on the phase information in a frequency domain, and the digital loop filter configured to output a result of the first low pass filtering as a digital code;
a digital controlled oscillator configured to output an oscillation signal having a second frequency, and the digital controlled oscillator configured to adjust a frequency of the oscillation signal based on the digital code;
a first divider configured to perform a first division to divide the second frequency of the oscillation signal based on a first division value, and the first divider configured to output a result of the first division as a division signal having a third frequency;
a second divider configured to perform a second division to divide the second frequency of the oscillation signal based on a second division value, and the second divider configured to output a result of the second division as an output signal having a final frequency;
a dithering block configured to perform, in cycles of the division signal, dithering on the first division value based on a pattern; and
a digital phase domain filter configured to perform second low pass filtering on the division signal in a phase domain, and the digital phase domain filter configured to output a result of the second low pass filtering as the feedback signal.

2. The digital phase locked loop of claim 1 , wherein the digital phase domain filter comprises:
a second digital phase detector configured to output second phase information based on a phase of the division signal and the phase of the feedback signal such that the second phase information indicates whether the phase of the feedback signal is advanced or delayed with respect to the phase of the division signal;
a second digital loop filter configured to perform third low pass filtering on the second phase information in the frequency domain, and the second digital loop filter configured to output a result of the third low pass filtering as a second digital code; and
a second digital controlled oscillator configured to adjust the first frequency of the feedback signal based on the second digital code.

3. The digital phase locked loop of claim 2 , wherein the digital phase detector and the second digital phase detector have a same structure.

4. The digital phase locked loop of claim 2 , wherein the digital loop filter and the second digital loop filter have a same structure.

5. The digital phase locked loop of claim 2 , wherein a first frequency range of the digital controlled oscillator is higher than a second frequency range of the second digital controlled oscillator.

6. The digital phase locked loop of claim 2 , wherein the second digital loop filter comprises:
a first amplifier configured to apply a first gain to the second phase information;
a second amplifier configured to apply a second gain to the second phase information;
an accumulator configured to accumulate outputs of the second amplifier; and
an adder configured to generate the second digital code by adding an output of the first amplifier and an output of the accumulator.

7. The digital phase locked loop of claim 6 , further comprising:
logic configured to adjust the first gain of the first amplifier and the second gain of the second amplifier.

8. The digital phase locked loop of claim 7 , further comprising:
an error detector configured to detect an error in the output signal by analyzing the phase information, and to generate error information based on the error, wherein
the logic is configured to adjust the first gain and the second gain based on the error information.

9. The digital phase locked loop of claim 8 , wherein
in a normal mode, if an amount of the error is greater than a threshold value, the logic is configured to enter a noise suppression mode to decrease the first gain and the second gain; and
in the noise suppression mode, if the amount of the error is less than or equal to the threshold value, the logic is configured to enter the normal mode to reset the first gain and the second gain.

10. The digital phase locked loop of claim 1 , wherein the dithering block is configured to,
store information about a modulation frequency and a modulation ratio, and
selectively instruct the first divider to modulate the third frequency of the division signal based on the modulation frequency and the modulation ratio.

11. A digital phase locked loop comprising:
a digital phase detector configured to output phase information based on a phase of a reference signal having a reference frequency and a phase of a feedback signal having a first frequency such that the phase information indicates whether the phase of the feedback signal is advanced or delayed with respect to the phase of the reference signal;
a digital loop filter configured to perform first low pass filtering on the phase information in a frequency domain, and the digital loop filter configured to output a result of the first low pass filtering as a digital code;
a digital controlled oscillator configured to output an oscillation signal having a second frequency, and the digital controlled oscillator configured to adjust a frequency of the oscillation signal depending on the digital code;
a first divider configured to perform a first division to divide the second frequency of the oscillation signal based on a first division value, and the first divider configured to output a result of the first division as a division signal having a third frequency;
a second divider configured to perform a second division to divide the second frequency of the oscillation signal based on a second division value, and the second divider configured to output a result of the second division as an output signal having a final frequency;
a dithering block configured to perform dithering, in cycles of the division signal, on the first division value based on a pattern;
a digital phase domain filter configured to perform second low pass filtering on the division signal in a phase domain, and the digital phase domain filter configured to output the result of the second low pass filtering as a filtered signal; and
a third divider configured to perform a third division to divide a frequency of the filtered signal based on a third division value, and the third divider configured to output a result of the third division as the feedback signal.

12. The digital phase locked loop of claim 11 , further comprising:
logic configured to adjust at least one of the first division value, the second division value, and the third division value.

13. The digital phase locked loop of claim 12 , wherein the logic is configured to adjust the first division value and the third division value such that a product of the first division value and the third division value is uniform.

14. The digital phase locked loop of claim 12 , further comprising:
an error detector configured to detect an error in the output signal by analyzing the phase information, wherein
the logic is configured to adjust the first division value and the third division value based on the error.

15. The digital phase locked loop of claim 14 , wherein in a normal mode, if an amount of

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yu Wonsik
• Kim Wooseok
• Kim Jihyun
• Kim Taeik
• Choo Kangyeop

Classifications

• H03L7/095 Primary

  using a lock detector (H03L7/087 takes precedence) · CPC title

• H03K5/135 Primary

  by the use of time reference signals, e.g. clock signals · CPC title

• H03L7/235 Primary

  Nested phase locked loops · CPC title

• H03L7/113

  using frequency discriminator · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title