Gold through silicon mask plating

Patent metadata

Field	Value
Publication number	US-12293943-B2
Application number	US-202017430617-A
Country	US
Kind code	B2
Filing date	Feb 13, 2020
Priority date	Feb 14, 2019
Publication date	May 6, 2025
Grant date	May 6, 2025

Abstract

Systems and methods are provided for method for etch assisted gold (Au) through silicon mask plating (EAG-TSM). An example method comprises providing a seed layer on a substrate and providing a silicon mask on at least a portion of the seed layer on the substrate. The silicon mask includes one or more via to be filled with Au. The masked substrate is subjected to at least one processing cycle, each processing cycle including an Au plating sub-step and an etch treatment sub-step. The cycles are repeated until a selected via fill thickness is achieved.

First claim

The invention claimed is:

1. A method for etch assisted gold (Au) through silicon mask plating (EAG-TSM), the method comprising:
providing a seed layer on a substrate;
providing a silicon mask on at least a portion of the seed layer on the substrate, the silicon mask including one or more via to be filled with Au;
subjecting the masked substrate to at least one processing cycle, each processing cycle including an Au electroplating sub-step and a chemical etch treatment sub-step; and
repeating the at least one processing cycle for a number of repeated cycles until a selected via fill thickness is achieved, wherein each repeat of the at least one processing cycle includes an alternation between the Au electroplating sub-step and the chemical etch treatment sub-step,
wherein in each Au electroplating sub-step, residual Au is deposited on the silicon mask along with a deposition of the Au in the one or more via, the residual Au partially blocking the one or more via; and
wherein in each chemical etch treatment sub-step, residual Au deposited on the silicon mask is etched away to unblock the one or more via for the deposition of the Au in the one or more via in the Au electroplating sub-step of a succeeding processing cycle.

2. The method of claim 1 , further comprising determining a via-fill efficiency based on a degree of via fill versus a degree of residual Au.

3. The method of claim 2 , further comprising adjusting the via-fill efficiency based on an inclusion of Sulphur trioxide (SO 3 ) in a chemistry of an Au electroplating solution in the electroplating sub-step.

4. The method of claim 2 , further comprising adjusting the via-fill efficiency based on an inclusion of cyanide (CN) in a chemistry of an Au electroplating solution in the electroplating sub-step.

5. The method of claim 1 , wherein an etchant in the chemical etch treatment sub-step includes I − (Iodide)/I 2 (Iodine) in a 6:1 molar ratio.

6. The method of claim 1 , wherein an etchant in the chemical etch treatment sub-step includes aqua-regia in a 1:3 molar ratio.

7. The method of claim 1 , wherein a cycle time of a first cycle in the number of repeated cycles is equal to a cycle time of another cycle in the number of repeated cycles.

8. The method of claim 1 , wherein a cycle time of a first cycle in the number of repeated cycles is not equal to a cycle time of another cycle in the number of repeated cycles.

9. The method of claim 1 , wherein a frequency of applying the chemical etch treatment sub-step during a first period of subjecting the masked substrate to the at least one processing cycle is different to a frequency of applying the chemical etch treatment sub-step during a second period of subjecting the masked substrate to the at least one processing cycle.

10. The method of claim 1 , wherein an Au electroplating solution used in the Au electroplating sub-step is different from an etchant used in the chemical etch treatment sub-step.

11. The method of claim 1 , wherein the Au electroplating sub-step and the chemical etch treatment sub-step are performed in two separate process modules.

12. The method of claim 1 , wherein the chemical etch treatment sub-step comprises:
delivering, via a set of nozzles, an etchant to the residual Au deposited on the silicon mask.

Assignees

• Lam Res Corp

Inventors

• Chua Lee Peng
• Liang Defu
• Blickensderfer Jacob Kurtis
• Ponnuswamy Thomas A
• Buckalew Bryan L
• Mayer Steven T

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/0595

  by using multiple deposition steps separated by etching steps · CPC title