Multilayer printed wiring board and method of manufacturing the same

US2018279486A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2018279486-A1
Application numberUS-201815987182-A
CountryUS
Kind codeA1
Filing dateMay 23, 2018
Priority dateNov 30, 2015
Publication dateSep 27, 2018
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A multilayer printed wiring board and a method of manufacturing the same are provided. A multilayer printed wiring board of the present embodiment includes: a core base material formed by laminating a first wiring layer and a first insulating layer in this order on an insulating substrate; and a built-up layer formed by laminating a second wiring layer and a second insulating layer in this order on the core base material. A primer layer is formed between the second wiring layer and the first insulating layer, the second wiring layer has a lower surface at least part of which is in contact with the primer layer, and the second wiring layer has an upper surface and a side surface on both of which a tin-plated layer and a silane coupling layer are formed in this order.

First claim

Opening claim text (preview).

What is claimed is: 1 . A multilayer printed wiring board, comprising; a core base material formed by laminating a first wiring layer and a first insulating layer in this order on an insulating substrate, and a built-up layer formed by laminating a second wiring layer and a second insulating layer in this order on the core base material, a primer layer formed between the second wiring layer and the first insulating layer; wherein the second wiring layer has a lower surface at least part of which is in contact with the primer layer; and wherein the second wiring layer has an upper surface and a side surface on both of which a tin-plated layer and a silane coupling layer are formed in this order. 2 . A multilayer printed wiring board, comprising: a core base material formed by laminating a first wiring layer and a first insulating layer in this order on an insulating substrate, and a built-up layer formed by laminating a second wiring layer and a second insulating layer in this order on the core base material, and, a primer layer formed between the second wiring layer and the first insulating layer; and, wherein the second wiring layer has a lower surface at least part of which is in contact with the primer layer; and wherein the second wiring layer has an upper surface and a side surface on both of which a silane coupling layer is formed. 3 . The multilayer printed wiring board of claim 1 , wherein the primer layer contains an epoxy resin. 4 . The multilayer printed wiring board of claim 1 , wherein the primer layer contains a polyimide resin or a polyamide resin. 5 . The multilayer printed wiring board of claim 1 , wherein the lower surface of the second wiring layer is in contact with the primer layer and the first wiring layer. 6 . The multilayer printed wiring board of claim 1 , wherein the second wring layer includes a copper electroless-plated layer contacting the primer layer, and a copper electroplated layer formed on the copper electroless-plated layer. 7 . A multilayer printed wiring board formed by, comprising: alternately lamination of at least one wiring layer and at least one insulating layer on an insulating substrate, a primer layer formed on at least one of the insulating layers; wherein the wiring layer is formed on at least one of the primer layers; wherein the wiring layer formed on the primer layer has a lower surface at least part of which is in contact with the primer layer; and wherein the wiring layer whose lower surface is in contact with the primer layer has an upper surface and a side surface on both of which a tin-plated layer and a silane coupling layer are formed in this order. 8 . A multilayer printed wiring board formed by alternately laminating at least one wiring layer and at least one insulating layer on an insulating substrate, characterized in that: a primer layer is formed on at least one of the insulating layers; the wiring layer is formed on at least one of the primer layers; the wiring layer formed on the primer layer has a lower surface at least part of which is in contact with the primer layer; and the wiring layer whose lower surface is in contact with the primer layer has an upper surface and a side surface on both of which a silane coupling layer is formed. 9 . A method of manufacturing a multilayer printed wiring board by forming a plurality of layers on a laminate by lamination of an insulating substrate and a first wiring layer formed on the insulating substrate, comprising: a first step of forming a first insulating layer on the laminate so as to cover the first wiring layer; a second step of forming a primer layer and a copper layer in this order on the first insulating layer, the primer layer increasing adhesion between the first insulating layer and the copper layer; a third step of forming via holes penetrating the copper layer, the primer layer, and the first insulating layer to expose a surface of the first wiring layer; a fourth step of performing desmear treatment for removing smears generated in the via holes; a fifth step of removing the copper layer and exposing a surface of the primer layer, following the fourth step; a sixth step of forming a copper electroless-plated layer on the surface of the primer layer and bottom surfaces and sidewall surfaces of the via holes, following the fifth step; a seventh step of forming a resist pattern on a surface of the copper electroless-plated layer in regions where a second wiring layer is not to be formed, the resist pattern serving as a plating mask; an eighth step of forming a copper electroplated layer on a surface of the copper electroless-plated layer in regions where the resist pattern has not been formed; a ninth step of peeling the resist pattern, following the eighth step; a tenth step of removing the copper electroless-plated layer in regions empty of the resist pattern, following the ninth step, to form a second wiring layer and expose the surface of the primer layer, the second wiring layer including the copper electroless-plated layer and the copper electroplated layer; an eleventh step of forming a tin-plated layer on a surface of the second wiring layer and then forming a silane coupling layer on a surface of the tin-plated layer; and a twelfth step of forming a second insulating layer so as to cover the primer layer and the second wiring layer where the tin-plated layer and the silane coupling layer have been formed. 10 . A method of manufacturing a multilayer printed wiring board including a plurality of layers formed on a laminate that is a lamination of an insulating substrate and a first wiring layer formed on the insulating substrate, comprising: a first step of forming a first insulating layer on the laminate so as to cover the first wiring layer; a second step of forming a primer layer and a copper layer in this order on the first insulating layer, the primer layer increasing adhesion between the first insulating layer and the copper layer; a third step of forming via holes penetrating the copper layer, the primer layer, and the first insulating layer to expose a surface of the first wiring layer; a fourth step of performing desmear treatment for removing smears generated in the via holes; a fifth step of removing the copper layer and exposing a surface of the primer layer, following the fourth step; a sixth step of forming a copper electroless-plated layer on the surface of the primer layer and bottom surfaces and sidewall surfaces of the via holes, following the fifth step; a seventh step of forming a resist pattern on a surface of the copper electroless-plated layer in regions where a second wiring layer is not to be formed, the resist pattern serving as a plating mask; an eighth step of forming a copper electroplated layer on a surface of the copper electroless-plated layer in regions where the resist pattern has not been formed; a ninth step of peeling the resist pattern, following the eighth step; a tenth step of removing the copper electroless-plated layer in regions empty of the resist pattern, following the ninth step, to form a second wiring layer and expose the surface of the primer layer, the second wiring layer including the copper electroless-plated layer and the copper electroplated layer; an eleventh step of forming a silane coupling layer on a surface of the second wiring layer; and a twelfth step of forming a second insulating layer so as to cover the primer layer and the second wiring layer where the silane coupling layer has been formed. 11 . A method of manufacturing a multilayer printed wiring board including a plurality of layers formed on a laminate that is a lamination of an

Assignees

Inventors

Classifications

  • H05K3/38Primary

    Improvement of the adhesion between the insulating substrate and the metal · CPC title

  • Removing material (B23K26/55, B23K26/57 take precedence) · CPC title

  • characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated · CPC title

  • Use of materials for the substrate · CPC title

  • characterised by the insulating layers or materials (H05K3/4688 takes precedence) · CPC title

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What does patent US2018279486A1 cover?
A multilayer printed wiring board and a method of manufacturing the same are provided. A multilayer printed wiring board of the present embodiment includes: a core base material formed by laminating a first wiring layer and a first insulating layer in this order on an insulating substrate; and a built-up layer formed by laminating a second wiring layer and a second insulating layer in this orde…
Who is the assignee on this patent?
Toppan Printing Co Ltd
What technology area does this patent fall under?
Primary CPC classification H05K3/38. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Sep 27 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).