Scan driving circuit and display device having the same

Patent metadata

Field	Value
Publication number	US-12293706-B2
Application number	US-202318530609-A
Country	US
Kind code	B2
Filing date	Dec 6, 2023
Priority date	Feb 22, 2023
Publication date	May 6, 2025
Grant date	May 6, 2025

Abstract

A scan driving circuit includes multiple stages. A j-th stage of the stages includes a buffer part electrically connected to an output terminal that operates in response to a potential of a first control node, a holding part electrically connected to the output terminal that operates in response to a potential of a second control node, and an inverter part electrically connected to the first and second control nodes that controls the potentials of the first and second nodes. The inverter part includes a control transistor including a gate electrically connected to the first control node, and a drain electrically connected to a first voltage terminal that receives a first low voltage or a second voltage terminal that receives a second low voltage. The control transistor includes a dummy gate that receives a low voltage lower than or equal to the first and second low voltages.

First claim

What is claimed is:

1. A scan driving circuit comprising a plurality of stages, each of the plurality of stages comprising:
a buffer part which is electrically connected to an output terminal and operates in response to a potential of a first control node;
a holding part which is electrically connected to the output terminal and operates in response to a potential of a second control node; and
an inverter part which is electrically connected to the first and second control nodes and controls the potentials of the first and second control nodes, wherein
the inverter part comprises: a control transistor including:
a gate electrically connected to the first control node; and
a drain electrically connected to a first voltage terminal that receives a first low voltage or a second voltage terminal that receives a second low voltage, and

the control transistor further includes a dummy gate that receives a low voltage lower than or equal to the first and second low voltages.

2. The scan driving circuit of claim 1 , wherein
a voltage level of the first low voltage is lower than a voltage level of the second low voltage, and
the dummy gate is electrically connected to the first voltage terminal.

3. The scan driving circuit of claim 1 , wherein the dummy gate is electrically connected to a third voltage terminal that receives a third low voltage having a voltage level lower than a voltage level of the first low voltage.

4. The scan driving circuit of claim 1 , wherein the control transistor comprises:
a first control transistor including a gate electrically connected to the first control node and electrically connected between an inverter voltage terminal and the second voltage terminal; and
a second control transistor including a gate electrically connected to the first control node and electrically connected between the second control node and the first voltage terminal.

5. The scan driving circuit of claim 4 , wherein
the first control transistor further includes a first dummy gate electrically connected to the first voltage terminal, and
the second control transistor further includes a second dummy gate electrically connected to the first voltage terminal.

6. The scan driving circuit of claim 5 , wherein a voltage level of the first low voltage is lower than a voltage level of the second low voltage.

7. The scan driving circuit of claim 4 , wherein
the first control transistor further includes a first dummy gate electrically connected to a third voltage terminal that receives a third low voltage, and
the second control transistor further includes a second dummy gate electrically connected to the third voltage terminal.

8. The scan driving circuit of claim 7 , wherein
a voltage level of the third low voltage is lower than a voltage level of the first low voltage, and
the voltage level of the first low voltage is lower than a voltage level of the second low voltage.

9. The scan driving circuit of claim 1 , wherein
the buffer part comprises a buffer transistor including a gate electrically connected to the first control node and electrically connected between a clock terminal and the output terminal, and
the holding part comprises a holding transistor including a gate electrically connected to the second control node and electrically connected between the output terminal and the second voltage terminal.

10. A display device comprising:
a plurality of pixels disposed on a base layer; and
a scan driving circuit disposed on the base layer and electrically connected to the plurality of pixels, wherein
the scan driving circuit comprises a plurality of stages,
each of the plurality of stages comprises:
a buffer part which is electrically connected to an output terminal and operates in response to a potential of a first control node;
a holding part which is electrically connected to the output terminal and operates in response to a potential of a second control node; and
an inverter part which is electrically connected to the first and second control nodes and controls the potentials of the first and second control nodes,

the inverter part comprises: a control transistor including:
a gate electrically connected to the first control node; and
a drain electrically connected to a first voltage terminal that receives a first low voltage or a second voltage terminal that receives a second low voltage, and

the control transistor further includes a dummy gate that receives a low voltage lower than or equal to the first and second low voltages.

11. The display device of claim 10 , wherein
a voltage level of the first low voltage is lower than a voltage level of the second low voltage, and
the dummy gate is electrically connected to the first voltage terminal.

12. The display device of claim 10 , wherein the dummy gate is electrically connected to a third voltage terminal that receives a third low voltage having a voltage level lower than a voltage level of the first low voltage.

13. The display device of claim 10 , wherein the control transistor comprises:
a first control transistor including a gate electrically connected to the first control node and electrically connected between an inverter voltage terminal and the second voltage terminal; and
a second control transistor including a gate electrically connected to the first control node and electrically connected between the second control node and the first voltage terminal.

14. The display device of claim 13 , wherein
the first control transistor further includes a first dummy gate electrically connected to the first voltage terminal, and
the second control transistor further includes a second dummy gate electrically connected to the first voltage terminal.

15. The display device of claim 14 , wherein a voltage level of the first low voltage is lower than a voltage level of the second low voltage.

16. The display device of claim 13 , wherein
the first control transistor further includes a first dummy gate electrically connected to a third voltage terminal that receives a third low voltage, and
the second control transistor further includes a second dummy gate electrically connected to the third voltage terminal.

17. The display device of claim 16 , wherein
a voltage level of the third low voltage is lower than a voltage level of the first low voltage, and
the voltage level of the first low voltage is lower than a voltage level of the second low voltage.

18. The display device of claim 10 , wherein
the buffer part comprises a buffer transistor including a gate electrically connected to the first control node and electrically connected between a clock terminal and the output terminal, and
the holding part comprises a holding transistor including a gate electrically connected to the second control node and electrically connected between the output terminal and the second voltage terminal.

19. The display device of claim 10 , wherein
each of the plurality of pixels comprises:
a light emitting element; and
a pixel circuit part electrically connected to the light emitting element, and

the pixel circuit part comprises:
at least one transistor; and
a shielding electrode overlapping a semiconductor pattern of the at least one transistor in a plan view.

20. The display device of claim 19 , wherein the dummy gate and the shielding electrode are disposed on a same layer.

21. An electronic device comprising a display device, the display device comprising:
a plurality of pixels disposed on a ba

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Eok Su
• KEUM Jongdo
• Kim Taesang

Classifications

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2300/0413

  Details of dummy pixels or dummy lines in flat panels · CPC title

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

• G09G2320/0214

  with crosstalk due to leakage current of pixel switch in active matrix panels · CPC title