Scan signal driver and a display device including the same

Patent metadata

Field	Value
Publication number	US-11238809-B2
Application number	US-202016901079-A
Country	US
Kind code	B2
Filing date	Jun 15, 2020
Priority date	Aug 23, 2019
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

A scan signal driver including: a plurality of stages for outputting scan signals and sensing signals, wherein a kth stage among the stages is connected to a kth scan signal line and a kth sensing signal line, and wherein the kth stage includes: a first output unit configured to output a scan clock signal input to a fit scan clock terminal to the kth scan signal line as a kth scan signal and to output a sensing clock signal input to a first sensing clock terminal to the kth sensing signal line as a k sensing signal when a pull-up node has a gate-on voltage; and a second output unit configured to output a carry clock signal input to a first carry clock terminal as a kth carry signal to a carry output terminal when the pull-up node has the gate-on voltage.

First claim

What is claimed is:

1. A scan signal driver, comprising:
a plurality of stages for outputting scan signals and sensing signals,
wherein a k th stage among the stages is connected to a k th scan signal line and a k th sensing signal line, and
wherein the k th stage comprises:
a first output unit configured to output a scan clock signal input to a first scan clock terminal to the k th scan signal line as a k th scan signal and to output a sensing clock signal input to a first sensing clock terminal to the k th sensing signal line as a k th sensing signal when a pull-up node has a gate-on voltage; and
a second output unit configured to output a carry clock signal input to a first carry clock terminal as a k th carry signal to a carry output terminal when the pull-up node has the gate-on voltage,

wherein a frame period comprises an active period and a vertical blank period, and
wherein the k th stage further comprises:
a sensing controller configured to apply the gate-on voltage to the pull-up node during the vertical blank period when a sensing control signal of the gate-on voltage is input to a sensing control terminal during the active period.

2. The scan signal driver of claim 1 , wherein the first output unit comprises:
a first scan pull-up transistor configured to be turned on by the gate-on voltage of the pull-up node to output the scan clock signal to the k th scan signal line; and
a first sensing pull-up transistor configured to be turned on by the gate-on voltage of the pull-up node to output the sensing clock signal to the k th sensing signal line.

3. The scan signal driver of claim 1 , wherein the second output unit comprises a carry pull-up transistor configured to be turned on by the gate-on voltage of the pull-up node to output the carry clock signal to the carry output terminal.

4. The scan signal driver of claim 1 , wherein the first output unit applies a first gate-off voltage to the k th scan signal line and the k th sensing line when a pull-down node has the gate-on voltage, and
wherein the second output unit applies the first gate-off voltage to the carry output terminal when the pull-down node has the gate-on voltage.

5. The scan signal driver of claim 4 , wherein the first output unit comprises:
a first scan pull-down transistor configured to be turned on by the gate-on voltage of the pull-down node to output the first gate-off voltage input to a first gate-off terminal to the k th scan signal line; and
a first sensing pull-down transistor configured to be turned on by the gate-on voltage of the pull-down node to output the first gate-off voltage of the first gate-off terminal to the k th sensing signal line.

6. The scan signal driver of claim 4 , wherein the second output unit comprises a carry pull-down transistor configured to be turned on by the gate-on voltage of the pull-down node to output the first gate-off voltage of the first gate-off terminal to the carry output terminal.

7. The scan signal driver of claim 4 , wherein the k stage comprises:
a third pull-up node controller configured to hold the pull-up node at the first gate-off voltage when the scan clock signal or the sensing clock signal has the gate-on voltage and the pull-down node has the gate-on voltage; and
an inverter configured to apply the first gate-off voltage to the pull-down node when the pull-up node has the gate-on voltage.

8. The scan signal driver of claim 7 , wherein the third pull-up node controller comprises:
a (10-1) th transistor configured to be turned on by the gate-on voltage of the scan clock signal or the gate-on voltage of the sensing clock signal to connect the pull-up node with the carry output terminal; and
a (10-2) th transistor configured to be turned on by the gate-on voltage of the pull-down node to connect the (10-1) th transistor with the carry output terminal.

9. The scan signal driver of claim 7 , wherein the third pull-up node controller comprises:
a (10-1) th transistor configured to be turned on by the gate-on voltage of the scan clock signal or the gate-on voltage of the sensing clock signal to connect the pull-up node with the carry output terminal; and
a (10-2) th transistor configured to be turned on by the gate-on voltage of the scan clock signal or the gate-on voltage of the sensing clock signal to connect the (10-1) th transistor with the carry output terminal.

10. The scan signal driver of claim 7 , wherein the inverter comprises:
an (11-1) th transistor configured to be turned on by the gate-on voltage of the pull-up node to apply the first gate-off voltage to the pull-down node;
an (11-2) th transistor configured to be turned on by the gate-on voltage of the pull-up node to connect the pull-down node with a (13-1) th transistor; and
a twelfth transistor configured to be turned on by the gate-on voltage of another carry clock signal input to a second carry clock terminal to apply the gate-on voltage to the pull-down node.

11. The scan signal driver of claim 7 , wherein the inverter comprises a thirteenth transistor configured to be turned on by the gate-on voltage of the pull-down node to apply the gate-on voltage to the pull-down node.

12. The scan signal driver of claim 7 , wherein the inverter further comprises: a fourteenth transistor configured to be turned on by the gate-on voltage of the pull-down node to apply the gate-on voltage between an (11-1) th transistor and an (11-2) th transistor.

13. The scan signal driver of claim 1 , wherein the sensing controller comprises:
a first transistor configured to be turned on by the gate-on voltage of the sensing control signal to apply the gate-on voltage to a sensing control node; and
a second transistor configured to be turned on by the gate-on voltage of the sensing control node to apply a first control clock signal input to a first control clock terminal to the pull-up node.

14. The scan signal driver of claim 13 , wherein the sensing controller further comprises a third transistor configured to be turned on by the gate-on voltage of the sensing control node to connect the second transistor with the pull-up node.

15. The scan signal driver of claim 13 , wherein the sensing controller comprises:
a third transistor configured to be turned on by a gate-on voltage of a second control clock signal input to a second control clock terminal to connect the second transistor with the first control clock terminal; and
a fourth transistor configured to be turned on by the gate-on voltage of the pull-up node to apply the gate-on voltage between the second transistor and the third transistor.

16. The scan signal driver of claim 13 , wherein the sensing controller further comprises:
a third transistor configured to be turned on by a gate-on voltage of a second control clock signal input to a second control clock terminal to connect the second transistor with the pull-up node; and
a fourth transistor configured to be turned on by the gate-on voltage of the pull-up node to apply the gate-on voltage between the second transistor and the third transistor.

17. The scan signal driver of claim 1 , wherein the sensing controller comprises:
a (1-1) th transistor configured to be turned on by the gate-on voltage of the sensing control signal to apply the gate-on voltage to a sensing control node;
a (1-2) th transistor configured to be turned on by the gate-on voltage of the sensing control signal to connect a third transistor with the sensing node; and
a fifth transistor configured to be turned on by the gate-on voltage of the sensing control no

Assignees

• Samsung Display Co Ltd

Inventors

• Park Jun Hyun
• Kim Dong Woo
• Lee An Su
• Jo Kang Moon

Classifications

• G09G2310/08

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• G09G3/3233

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• G09G3/3275

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• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title