Scan driver and display device having the same

Patent metadata

Field	Value
Publication number	US-11127339-B2
Application number	US-202016875682-A
Country	US
Kind code	B2
Filing date	May 15, 2020
Priority date	May 23, 2019
Publication date	Sep 21, 2021
Grant date	Sep 21, 2021

Abstract

A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

First claim

What is claimed is:

1. A scan driver comprising:
a plurality of stages,
wherein an nth (n is a natural number) stage from among the stages comprises:
a first input circuit configured to control a voltage of a first node in response to a carry signal of a previous stage of the nth stage, which is supplied to a first input terminal;
a second input circuit configured to control the voltage of the first node in response to a carry signal of a next stage of the nth stage, which is supplied to a second input terminal;
a first output circuit configured to output, to a first output terminal, an nth carry signal corresponding to a carry clock signal supplied to a first clock terminal in response to the voltage of the first node;
a second output circuit configured to output, to a second output terminal, an nth scan signal corresponding to a scan clock signal supplied to a second clock terminal in response to the voltage of the first node, and output, to a third output terminal, an nth sensing signal corresponding to a sensing clock signal supplied to a third clock terminal in response to the voltage of the first node; and
a sampling circuit configured to store the carry signal of the previous stage in response to a first select signal supplied to a first control terminal, and configured to supply a control voltage supplied through a reference power terminal to the first node in response to a second select signal supplied to a second control terminal and the stored carry signal of the previous stage, and
wherein the sampling circuit comprises:
a first transistor coupled between the first input terminal and a first control node, the first transistor comprising a gate electrode coupled to the first control terminal;
a capacitor coupled between the first control node and the reference power terminal;
a second transistor coupled between the reference power terminal and a second control node, the second transistor comprising a gate electrode coupled to the first control node; and
a third transistor coupled between the second control node and the first node, the third transistor comprising a gate electrode coupled to the second control terminal.

2. The scan driver of claim 1 , wherein the first transistor comprises a first sub-transistor and a second sub-transistor, which are coupled in series to each other, and
wherein one electrode of the first sub-transistor and one electrode of the second sub-transistor are coupled to the second control node.

3. The scan driver of claim 1 , further comprising:
a feedback circuit configured to supply the nth scan signal or the nth sensing signal to the first input circuit and the second input circuit.

4. The scan driver of claim 1 , wherein each of the first input circuit, the second input circuit, the first output circuit, the second output circuit, and the sampling circuit comprises an oxide semiconductor transistor.

5. The scan driver of claim 4 , wherein the control voltage is a gate-on voltage to turn on the oxide semiconductor transistor.

6. The scan driver of claim 1 , further comprising:
a feedback circuit configured to supply the control voltage to the first input circuit and the second input circuit in response to the voltage of the first node.

7. The scan driver of claim 6 , wherein the first input circuit comprises:
a fifth transistor comprising a first electrode coupled to the reference power terminal, a second electrode coupled to a feedback node, and a gate electrode coupled to the first input terminal; and
a sixth transistor comprising a first electrode coupled to the feedback node, a second electrode coupled to the first node, and a gate electrode coupled to the first input terminal, and
wherein the feedback circuit comprises a seventh transistor comprising a first electrode coupled to the reference power terminal, a second electrode coupled to the feedback node, and a gate electrode coupled to the first node.

8. The scan driver of claim 1 , wherein the sampling circuit is configured to discharge the first node in response to a scan start signal supplied to a third control terminal.

9. The scan driver of claim 8 , wherein the sampling circuit further comprises a fourth transistor coupled between a first power terminal to which a first power source is applied and the first node, the fourth transistor comprising a gate electrode coupled to the third control terminal, and
wherein the first power source has a voltage level lower than a voltage level of the control voltage.

10. The scan driver of claim 9 , wherein a stage that receives a carry signal of the previous stage, which has a pulse overlapping with a pulse of the first select signal, from among the stages is selected, and
wherein the selected stage is configured to output the sensing signal corresponding to the sensing clock signal, after a pulse of the second select signal is applied.

11. The scan driver of claim 9 , wherein the stages are initialized in response to a scan start signal corresponding to the carry signal of the previous stage.

12. A scan driver of claim 6 , comprising:
a plurality of stages,
wherein an nth (n is a natural number) stage from among the stages comprises:
a first input circuit configured to control a voltage of a first node in response to a carry signal of a previous stage of the nth stage, which is supplied to a first input terminal;
a second input circuit configured to control the voltage of the first node in response to a carry signal of a next stage of the nth stage, which is supplied to a second input terminal;
a first output circuit configured to output, to a first output terminal, an nth carry signal corresponding to a carry clock signal supplied to a first clock terminal in response to the voltage of the first node;
a second output circuit configured to output, to a second output terminal, an nth scan signal corresponding to a scan clock signal supplied to a second clock terminal in response to the voltage of the first node, and output, to a third output terminal, an nth sensing signal corresponding to a sensing clock signal supplied to a third clock terminal in response to the voltage of the first node; and
a sampling circuit configured to store the carry signal of the previous stage in response to a first select signal supplied to a first control terminal, and configured to supply a control voltage supplied through a reference power terminal to the first node in response to a second select signal supplied to a second control terminal and the stored carry signal of the previous stage,
a feedback circuit configured to supply the control voltage to the first input circuit and the second input circuit in response to the voltage of the first node, and
wherein the first input circuit comprises:
a fifth transistor comprising a first electrode coupled to the first input terminal, a second electrode coupled to a feedback node, and a gate electrode coupled to the first input terminal; and
a sixth transistor comprising a first electrode coupled to the feedback node, a second electrode coupled to the first node, and a gate electrode coupled to the first input terminal, and
wherein the feedback circuit comprises a seventh transistor comprising a first electrode coupled to the reference power terminal, a second electrode coupled to the feedback node, and a gate electrode coupled to the first node.

13. The scan driver of claim 12 , wherein the second input circuit is configured to control the voltage of the first node in response to a voltage of a second node, and
wherein the second input circuit comprises:
a ninth transistor comprising a first electrode coupled to the first node, a second electrode

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Kang Nam
• Lim Sung Hoon
• Lee Woo Geun
• Cho Kyu Sik
• Choi Jae Beom

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/2092 Primary

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title