Method of fabricating transistors and stacked planar capacitors for memory and logic applications

Patent metadata

Field	Value
Publication number	US-12289894-B1
Application number	US-202217807655-A
Country	US
Kind code	B1
Filing date	Jun 17, 2022
Priority date	Jun 17, 2022
Publication date	Apr 29, 2025
Grant date	Apr 29, 2025

Abstract

A method of fabricating a system includes fabricating a plurality of transistors and coupling a forming a bridge structure connected between a gate contact of a first transistor with a drain contact of a second transistor. The method further includes fabricating a multi-level memory structure including capacitors that comprise a ferroelectric material or a paraelectric material. The capacitors within a given level are coupled together by a plate electrode. The method further includes forming a signal electrode coupled with the plate electrode.

First claim

What is claimed is:

1. A method of fabricating a system, the method comprising:
fabricating a plurality of transistors within a first level, wherein individual ones of the plurality of transistors comprise a source, a drain, and a gate between the source and the drain, a drain contact coupled with the drain and a gate contact coupled with the gate;
forming a bridge structure connected between the gate contact of a first transistor in the plurality of transistors to the drain contact of a second transistor in the plurality of transistors;
forming a first plate electrode above and coupled with the bridge structure;
forming a first plurality of trench capacitors within a first dielectric on the first plate electrode wherein individual ones of the first plurality of trench capacitors comprise a first dielectric layer comprising a perovskite material;
forming a signal electrode on the first plate electrode between a pair of trench capacitors of the individual ones of the first plurality of trench capacitors;
forming a second plate electrode above and coupled with the signal electrode; and
forming a second plurality of trench capacitors within a second dielectric on the second plate electrode wherein individual ones of the second plurality of trench capacitors comprise a second dielectric layer comprising the perovskite material.

2. The method of claim 1 , wherein prior to forming the first plate electrode, the method further comprises:
forming a conductive interconnect coupled with the bridge structure;
forming a first electrode structure on the conductive interconnect by forming an opening in a first etch stop layer deposited on the conductive interconnect and by filling the opening with a conductive material; and
depositing a first conductive layer on the first electrode structure,
wherein forming the first plate electrode further comprises etching the first conductive layer.

3. The method of claim 2 , wherein prior to forming the second plate electrode, the method further comprises:
forming a second electrode structure on the signal electrode by forming an opening in a second etch stop layer deposited on the signal electrode and by filling the opening with the conductive material; and
depositing a second conductive layer on the signal electrode,
wherein forming the second plate electrode further comprises etching the second conductive layer.

4. The method of claim 1 , wherein forming the first plurality of trench capacitors comprises:
etching the first dielectric to form a first plurality of trenches, and exposing first portions of the first plate electrode;
forming a first dielectric spacer on sidewalls of individual ones of the first plurality of trenches;
depositing a first electrode layer on a first base of the individual ones of the first plurality of trenches and adjacent to the first dielectric spacer, wherein the first electrode layer comprises a first conductive layer;
depositing the first dielectric layer comprising the perovskite material on the first electrode layer; and
depositing a second electrode layer on the first dielectric layer, wherein the second electrode layer comprises a second conductive layer.

5. The method of claim 4 , wherein forming the second plurality of trench capacitors comprises:
etching the second dielectric to form a second plurality of trenches, and exposing second portions of the second plate electrode;
forming a second dielectric spacer on sidewalls of individual ones of the second plurality of trenches;
depositing a third electrode layer on a second base of the individual ones of the second plurality of trenches and adjacent to the second dielectric spacer, wherein the third electrode layer comprises the first conductive layer;
depositing the second dielectric layer comprising the perovskite material on the third electrode layer; and
depositing a fourth electrode layer on the second dielectric layer, wherein the fourth electrode layer comprises the second conductive layer.

6. The method of claim 1 further comprising:
forming a first plurality of via electrodes, wherein individual ones of the first plurality of via electrodes are formed on the individual ones of the first plurality of trench capacitors by depositing a third dielectric on the first plurality of trench capacitors and on the first dielectric and forming a first plurality of openings in the third dielectric; and
forming a second plurality of via electrodes, wherein individual ones of the second plurality of via electrodes are formed on the individual ones of the second plurality of trench capacitors by depositing a fourth dielectric on the second plurality of trench capacitors and on the second dielectric and forming a second plurality of openings in the third dielectric.

7. The method of claim 6 , further comprising forming a plurality of conductive vias, wherein individual ones of the plurality of conductive vias are formed on the individual ones of the first plurality of via electrodes, and on the signal electrode, and wherein forming the plurality of conductive vias further comprises depositing a fifth dielectric on the third dielectric, and etching a third plurality of openings in the fifth dielectric.

8. The method of claim 7 , wherein immediately after forming the plurality of conductive vias and prior to forming the second plate electrode, the method further comprises:
depositing a second etch stop layer above the plurality of conductive vias;
forming a second electrode structure coupled with a conductive via in the plurality of conductive vias formed on the signal electrode, wherein forming the second electrode structure comprises forming an opening in the second etch stop layer and by filling the opening with a conductive material; and
planarizing to form the second electrode structure.

9. The method of claim 1 , wherein forming the signal electrode further comprises forming between an equal number of trench capacitors in the first plurality of trench capacitors on either side of the signal electrode.

10. The method of claim 5 , wherein forming the first dielectric spacer comprises:
conformally depositing a first insulator layer comprising silicon nitride, carbon doped silicon nitride, Al x O y , HfO x , ZrO x , TaO x , TiO x , AlSiO x , HfSiO x , or TaSiO x on the first base and on the sidewalls of the individual ones of the first plurality of trenches; and
etching and removing the first insulator layer from the first base,
wherein forming the second dielectric spacer comprises:
conformally depositing a second insulator layer comprising silicon nitride, carbon doped silicon nitride, Al x O y , HfO x , ZrO x , TaO x , TiO x , AlSiO x , HfSiO x , or TaSiO x on the second base and on the sidewalls of the individual ones of the second plurality of trenches; and
etching and removing the second insulator layer from the second base.

11. The method of claim 1 , wherein depositing the perovskite material comprises depositing one of:
bismuth ferrite (BFO) or BFO with a first doping material, where in the first doping material is one of lanthanum or elements from lanthanide series of periodic table;
lead zirconium titanate (PZT) or PZT with a second doping material, wherein the second doping material is one of La or Nb;
a relaxor ferroelectric material which includes one of: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or Barium titanium-barium strontium titanium (BT-BST);
a perovskite material which includes one of: BaTiO 3 , PbTiO 3 , KNbO 3 , or NaTaO 3 ; hexagonal ferroelectric which

Assignees

• Kepler Computing Inc

Inventors

• Dokania Rajeev Kumar
• Sato Noriyuki
• Rios Rafael
• Mathuriya Amrita
• Mukherjee Niloy
• Rathi Somilkumar J
• Manipatruni Sasikanth
• Gosavi Tanay

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10B12/315

  with the capacitor higher than a bit line · CPC title

• H10D1/682

  having dielectrics comprising perovskite structures · CPC title

• H10D1/716

  having vertical extensions · CPC title