Analog-to-digital converting circuit using auto-zero period optimization and operation method thereof

Patent metadata

Field	Value
Publication number	US-12289116-B2
Application number	US-202217971690-A
Country	US
Kind code	B2
Filing date	Oct 24, 2022
Priority date	Nov 15, 2021
Publication date	Apr 29, 2025
Grant date	Apr 29, 2025

Abstract

A circuit includes a first amplifier that first compares a ramp signal and a reset signal of a pixel signal output from a pixel array in a first operation period, second compares the ramp signal and an image signal of the pixel signal in a second operation period, and generates a first output signal in the first and second operation periods based on first and second comparison results; and a second amplifier that charges a capacitor in response to a second auto-zero signal in a second auto-zero period, stops an operation of the second amplifier from a time point at which the second auto-zero period ends to a time point at which the first operation period starts, and generates a second output signal based on the first output signal in the first operation period and the second operation period.

First claim

What is claimed is:

1. A circuit comprising:
a first amplifier configured to:
equalize voltage levels of input nodes and an output node of the first amplifier in response to a first auto-zero signal in a first auto-zero period,
receive a ramp signal at a first input node of the input nodes, and a pixel signal output from a pixel array at a second input node of the input nodes through a column line of the pixel array, the column line connected to the second input node of the first amplifier,
first compare the ramp signal and a reset signal of the pixel signal in a first operation period,
second compare the ramp signal and an image signal of the pixel signal in a second operation period after the first operation period, and
generate a first output signal on the output node in the first and second operation periods based on the first and second comparison results; and

a second amplifier including an input node connected to the output node of the first amplifier, and the second amplifier configured to:
charge a capacitor in response to a second auto-zero signal different from the first auto-zero signal in a second auto-zero period,
stop operation of the second amplifier from a time point at which the second auto-zero period ends to a time point at which the first operation period starts,
receive the first output signal from the first amplifier at the input node of the second amplifier, and
generate a second output signal based on the first output signal from the first amplifier in the first operation period and the second operation period,
wherein the second auto-zero period overlaps the first auto-zero period, and
wherein, when the operation of the second amplifier is stopped, the circuit is configured such that the second amplifier is blocked from providing a power supply voltage from the time point at which the second auto-zero period ends to the time point at which the first operation period starts.

2. The circuit of claim 1 , wherein a length of the second auto-zero period is determined based on a time taken for the capacitor to be fully charged and is shorter than a length of the first auto-zero period.

3. The circuit of claim 1 , wherein the second amplifier includes:
a first transistor configured to provide the power supply voltage to a first output node, from which the second output signal is output, in response to the first output signal;
a second transistor connected to the capacitor through a bias node, and configured to turn on in response to the second auto-zero signal;
a current source connected to the first transistor through the first output node, connected to the capacitor and the second transistor through the bias node, and configured to generate a power current based on a voltage level of the bias node, which is maintained by the capacitor; and
a third transistor connected to the first transistor, and configured to provide the power supply voltage to the first transistor and turn off in response to a power down signal such that the operation of the second amplifier is stopped.

4. The circuit of claim 3 , wherein the third transistor is configured to:
turn off in response to the power down signal being activated when the second auto-zero period ends, and
turn on in response to the power down signal being deactivated when the first operation period starts.

5. The circuit of claim 3 , wherein the first transistor and the third transistor are PMOS transistors, and the second transistor is an NMOS transistor.

6. The circuit of claim 3 , wherein the second amplifier further includes:
a feedback circuit connected to the first output node, and configured to receive the second output signal, and to output a feedback signal; and
a fourth transistor connected to the current source through a second output node, and configured to electrically connect the first output node to the second output node in response to the feedback signal.

7. The circuit of claim 6 , wherein the feedback circuit includes a logic gate configured to output the feedback signal based on the second output signal and a feedback enable signal, and
wherein the fourth transistor is turned off in response to the feedback signal.

8. The circuit of claim 7 , wherein the fourth transistor is an NMOS transistor, and the logic gate is a NAND gate.

9. The circuit of claim 6 , wherein the second amplifier further includes:
a control circuit configured to output a control current in response to a control signal,
wherein the control circuit includes:
a fifth transistor configured to generate the control current based on the power supply voltage, in response to the control signal; and
a sixth transistor configured to provide the control current to the first output node in response to a bias signal.

10. The circuit of claim 9 , wherein, during the first operation period or the second operation period, when the ramp signal starts to ramp down, the control circuit outputs the control current to the current source through the first output node and the second output node.

11. An operation method of an analog-to-digital converting circuit including a first amplifier and a second amplifier, the method comprising:
equalizing voltage levels of input nodes and an output node of the first amplifier in response to a first auto-zero signal in a first auto-zero period;
charging a capacitor of the second amplifier in response to a second auto-zero signal in a second auto-zero period overlapping the first auto-zero period;
stopping operation of the second amplifier from a time point at which the second auto-zero period ends to a time point at which a first operation period starts;
receiving a pixel signal output from a pixel array at an input node of the input nodes of the first amplifier through a column line of the pixel array, the column line connected to the input node of the first amplifier;
generating a first output signal from the output node of the first amplifier by comparing a ramp signal and a reset signal of the pixel signal during the first operation period and comparing the ramp signal and an image signal of the pixel signal during a second operation period after the first operation period;
receiving the first output signal from the first amplifier at an input node of the second amplifier, the input node of the second amplifier connected to the output node of the first amplifier; and
generating a second output signal from an output node of the second amplifier based on the first output signal from the first amplifier in the first and second operation periods,
wherein the stopping of the operation of the second amplifier includes:
blocking a supply of a power supply voltage to the second amplifier from the time point at which the second auto-zero period ends to the time point at which the first operation period starts.

12. The method of claim 11 , wherein the charging of the capacitor of the second amplifier includes determining a length of the second auto-zero period based on a time taken for the capacitor to be fully charged,
wherein the length of the second auto-zero period is shorter than a length of the first auto-zero period, and
wherein the stopping of the operation of the second amplifier is performed in response to a power down signal being activated when the second auto-zero period ends and being deactivated when the first operation period starts.

13. The method of claim 11 , further comprising:
controlling a power current of the analog-to-digital converting circuit by using the second output signal,
wherein the controlling of the power current is performed during at least one operation period of the first operation period and the secon

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jun Jaehoon

Classifications

• H04N25/75

  Circuitry for providing, modifying or processing image signals from the pixel array · CPC title

• H04N25/772

  comprising A/D, V/T, V/F, I/T or I/F converters · CPC title

• H03F2203/45534

  the FBC comprising multiple switches and being coupled between the LC and the IC · CPC title

• H03F3/45183

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title

• H03F3/087

  with IC amplifier blocks (H03F3/085 takes precedence) · CPC title