Amplifier, and analog-to-digital conversion circuit and image sensor including the same

Patent metadata

Field	Value
Publication number	US-10616518-B2
Application number	US-201816008186-A
Country	US
Kind code	B2
Filing date	Jun 14, 2018
Priority date	Oct 16, 2017
Publication date	Apr 7, 2020
Grant date	Apr 7, 2020

Abstract

An analog-to-digital conversion circuit includes a first amplifier that generates a first output signal by comparing a pixel signal output from a pixel array with a ramp signal, and a second amplifier that generates a comparison signal based on the first output signal. The first amplifier includes a first current source that generates a first bias current in a first operation period and a second operation period, and a second current source that generates a second bias current in the first operation period. The analog-to-digital conversion circuit converts an analog signal output from the pixel array into a digital signal.

First claim

What is claimed is:

1. An analog-to-digital conversion circuit, comprising:
a first amplifier that generates a first output signal by comparing a pixel signal output from a pixel array with a ramp signal; and
a second amplifier that generates a comparison signal based on the first output signal,
wherein the first amplifier comprises:
a first current source that generates a first bias current in a first operation period and a second operation period; and
a second current source that generates a second bias current in the first operation period,

wherein the analog-to-digital conversion circuit converts an analog signal output from the pixel array into a digital signal.

2. The analog-to-digital conversion circuit according to claim 1 , wherein the first current source sinks the first bias current, and the second current source generates the second bias current.

3. The analog-to-digital conversion circuit according to claim 1 , wherein an amount of the second bias current is less than an amount of the first bias current.

4. The analog-to-digital conversion circuit according to claim 1 , wherein the first amplifier further comprises:
an input stage comprising a first input and a second input, wherein the first input receives the ramp signal and the second input receives the pixel signal; and
an output stage comprising a first output node and a second output node, wherein the output stage generates an output signal based on a voltage difference between the first input and the second input,
wherein a static current flowing through the input stage is less than the first bias current in the first operation period, and the static current flowing through the input stage is about equal to the first bias current in the second operation period.

5. The analog-to-digital conversion circuit according to claim 4 , wherein, in the first operation period, the first input is connected to the second output node, and the second input is connected to the first output node.

6. The analog-to-digital conversion circuit according to claim 4 , wherein the output stage further comprises:
a first transistor comprising a drain and a gate, wherein the drain of the first transistor is connected to the first output node and the gate of the first transistor is connected to the second output node; and
a second transistor comprising a drain and a gate, wherein the drain of the second transistor and the gate of the second transistor are connected to the second output node,
wherein the second current source comprises:
a bias transistor comprising a gate connected to the second output node; and
a switching transistor connected between the bias transistor and the first current source.

7. The analog-to-digital conversion circuit according to claim 1 , wherein the first amplifier performs an operation of comparing the pixel signal with the ramp signal in the second operation period, and the second current source is turned off in the second operation period.

8. The analog-to-digital conversion circuit according to claim 1 , wherein the first current source and the second current source are connected to a common node,
a first power supply voltage is applied to the first current source,
a second power supply voltage is applied to the second current source, and
a level of the second power supply voltage is higher than a level of the first power supply voltage.

9. The analog-to-digital conversion circuit according to claim 1 , wherein the first current source and the second current source are connected to a common node,
a first power supply voltage is applied to the first current source,
a second power supply voltage is applied to the second current source, and
a level of the second power supply voltage is lower than a level of the first power supply voltage.

10. The analog-to-digital conversion circuit according to claim 1 , wherein a third bias current of the second amplifier is set based on a difference between the first bias current and the second bias current.

11. An amplifier, comprising:
a first current source that generates a first bias current based on a first power supply voltage in a first operation period and a second operation period;
a second current source that generates a second bias current based on a second power supply voltage in the first operation period, wherein the second current source is turned off in the second operation period;
an input stage that receives a pixel signal and a ramp signal; and
an output stage that outputs a comparison signal generated based on a level difference between the pixel signal and the ramp signal.

12. The amplifier according to claim 11 , wherein a level of the first power supply voltage is lower than a level of the second power supply voltage.

13. The amplifier according to claim 11 , wherein an amount of the second bias current is less than an amount of the first bias current.

14. The amplifier according to claim 11 , wherein the first current source sinks the first bias current, and the second current source generates the second bias current.

15. The amplifier according to claim 11 , wherein the input stage is operated based on a third bias current corresponding to a difference between the first bias current and the second bias current in the first operation period, and the input stage is operated based on the first bias current in the second operation period.

16. An image sensor, comprising:
a pixel array comprising a plurality of pixels; and
a comparison circuit that compares a pixel signal output from the pixel array with a ramp signal,
wherein the comparison circuit operates in an auto-zero period based on a first bias current, and operates in a comparison operation period based on a second bias current that is different from the first bias current.

17. The image sensor according to claim 16 , wherein the comparison circuit comprises:
a first amplifier that operates in the auto-zero period based on the first bias current; and that operates in the comparison operation period based on the second bias current; and
a second amplifier that operates in the auto-zero period and the comparison operation period based on a third bias current that is proportional to the first bias current.

18. The image sensor according to claim 17 , wherein the first amplifier comprises:
a first current source that generates the second bias current in the auto-zero period and the comparison operation period; and
a second current source that generates a fourth bias current in the auto-zero period,
wherein a difference between the second bias current and the first bias current is about equal to the fourth bias current.

19. The image sensor according to claim 18 , wherein the second current source is turned off in the comparison operation period.

20. The image sensor according to claim 16 , further comprising:
a counter circuit that counts an output signal of the comparison circuit,
wherein the comparison circuit and the counter circuit perform a correlated double sampling operation.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Yun-Hwan
• Kang Sun-Yool

Classifications

• H03F2200/129

  there being a feedback over the complete amplifier · CPC title

• H03M1/56

  Input signal compared with linear ramp · CPC title

• H03F2203/45536

  the FBC comprising a switch and being coupled between the LC and the IC · CPC title

• H03F1/0211

  with control of the supply voltage or current · CPC title

• H03F3/4521

  Complementary long tailed pairs having parallel inputs and being supplied in parallel · CPC title