Analog-to-digital conversion circuit, and image sensor including the same

Patent metadata

Field	Value
Publication number	US-9282264-B2
Application number	US-201414303221-A
Country	US
Kind code	B2
Filing date	Jun 12, 2014
Priority date	Sep 7, 2012
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

One embodiment of an analog-to-digital converter includes at least one comparator and a restriction circuit. The comparator has first and second input nodes and a connection node. The connection node is one of an internal node and an output node of the comparator. The restriction circuit is electrically connected to the connection node, and the restriction circuit is configured to restrict a voltage of the connection node.

First claim

The invention claimed is:

1. An image sensor, comprising:
a pixel array configured to generate at least one pixel signal;
a ramp generator configured to generate a ramp signal; and
an analog-to-digital converter configured to receive the ramp signal and the pixel signal, and generate a digital signal representing the pixel signal, the analog-to-digital converter including,
at least one comparator, the comparator having an output node configured to output a comparison result signal; and
a restriction circuit electrically connected to the output node, the restriction circuit including a switch and a diode, the switch connected in series to the diode, the restriction circuit configured to suppress a change in total current by creating a current path between the output node and one of a ground and a power supply if the comparison result signal changes, the total current being a current flowing through the comparator plus a current flowing through the restriction circuit.

2. The image sensor of claim 1 , wherein the switch is configured to disable the restriction circuit during an initial operation period of the first comparator.

3. The image sensor of claim 1 , wherein the at least one comparator is configured to compare the ramp signal and the at least one pixel signal, and to output a comparison result signal.

4. The image sensor of claim 3 , wherein the restriction circuit is configured to restrict the comparison result signal.

5. An image sensor, comprising:
a pixel array configured to generate at least one pixel signal;
a ramp generator configured to generate a ramp signal; and
an analog-to-digital converter configured to receive the ramp signal and the pixel signal, and generate a digital signal representing the pixel signal, the analog-to-digital converter including at least one comparing circuit, the comparing circuit including,
a first comparator having a first output node,
a second comparator having input nodes and a second output node, one of the input nodes connected to the first output node of the first comparator, and
a first restriction circuit electrically connected to the second output node, the restriction circuit configured to restrict a voltage at the second output node by creating a current path between the second output node and one of ground and a power supply line if the voltage at the second output node is one of higher or lower than a threshold value.

6. The image sensor of claim 5 , wherein the first restriction circuit includes a diode.

7. The image sensor of claim 6 , wherein the first restriction circuit includes a switch connected in series to the diode.

8. The image sensor of claim 7 , wherein the switch is configured to disable the restriction circuit during an initial operation period of the second comparator.

9. The image sensor of claim 5 , wherein
the first comparator includes an amplifier having first and second first stage output nodes, at least one of the first and second first stage output nodes serving as the first output node; and
the comparing circuit includes a second restriction circuit, the second restriction circuit being electrically connected between the first and second first stage output nodes of the amplifier, the second restriction circuit configured to restrict a voltage at the first output node of the first comparator by creating a current path between the first output node and one of ground and a power supply line if the voltage at the first output node is one of higher or lower than a threshold value.

10. The image sensor of claim 5 , wherein the first comparator is configured to compare the ramp signal and the at least one pixel signal, and to output a comparison result signal.

11. The image sensor of claim 10 , wherein the first restriction circuit is configured to restrict the comparison result signal.

12. An image sensor, comprising:
a pixel array configured to generate at least one pixel signal;
a ramp generator configured to generate a ramp signal; and
an analog-to-digital converter configured to receive the ramp signal and the pixel signal, and generate a digital signal representing the pixel signal, the analog-to-digital converter including,
a first comparator, the first comparator including an amplifier, the amplifier including,
a first output node between a first PMOS transistor and a first NMOS transistor connected in series between a power supply voltage and a common node, and
a second output node between a second PMOS transistor and a second NMOS transistor connected in series between the power supply voltage and the common node; and

a restriction circuit connected between the first and second output nodes, the restriction circuit configured to suppress a change in current flowing through the amplifier when a voltage at the common node falls below a saturation voltage of the first and second NMOS transistors such that a low level of the voltage at the common node is restricted by the pixel signal.

13. The image sensor of claim 12 , wherein the restriction circuit includes a diode.

14. The image sensor of claim 13 , wherein the diode is a diode connected PMOS transistor.

15. The image sensor of claim 12 , wherein the restriction circuit includes a transistor.

16. The image sensor of claim 12 , wherein the first comparator is configured to compare the ramp signal and the at least one pixel signal, and to output a comparison result signal.

17. The image sensor of claim 16 , wherein the restriction circuit is configured to restrict the comparison result signal.

18. The image sensor of claim 12 , wherein the restriction circuit includes a switch.

Assignees

• Park Yu Jin
• Yang Han
• Lim Sin-Hwan
• Choo Kyo Jin
• Ham Seog Heon
• Samsung Electronics Co Ltd

Inventors

• Park Yu Jin
• Yang Han
• Lim Sin-Hwan
• Choo Kyo Jin
• Ham Seog Heon

Classifications

• H04N25/677 Primary

  for reducing the column or line fixed pattern noise · CPC title

• H04N25/65

  applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS · CPC title

• H04N25/767

  Horizontal readout lines, multiplexers or registers · CPC title

• H04N25/621

  for the control of blooming · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title