Contact structures for three-dimensional memory devices and methods for forming the same

Patent metadata

Field	Value
Publication number	US-12283547-B2
Application number	US-202217655256-A
Country	US
Kind code	B2
Filing date	Mar 17, 2022
Priority date	Feb 22, 2021
Publication date	Apr 22, 2025
Grant date	Apr 22, 2025

Abstract

The present disclosure describes a three-dimensional (3D) memory device includes first and second memory arrays disposed on a semiconductor layer. The 3D memory device can also include a staircase structure disposed between the first and second memory arrays. The staircase structure includes first and second staircase regions. The first staircase region includes a first staircase structure that contains a first plurality of stairs descending in a first direction. The second staircase region includes a second staircase structure that contains a second plurality of stairs descending in a second direction. The 3D memory device can also include a contact region disposed between the first and second staircase regions. The contact region includes a plurality of contacts the extending through an insulating layer and into the semiconductor layer.

First claim

What is claimed is:

1. A three-dimensional (3D) memory device, comprising:
first and second memory arrays disposed on a semiconductor layer;
a staircase structure disposed between the first and second memory arrays, wherein:
the staircase structure includes first and second staircase regions;
the first staircase region includes a first staircase structure, wherein the first staircase structure includes a first plurality of stairs descending in a first direction; and
the second staircase region includes a second staircase structure, wherein the second staircase structure includes a second plurality of stairs descending in a second direction; and

a contact region disposed between the first staircase region and the second staircase region, wherein the contact region includes a through silicon contact (TSC) structure extending through an insulating layer and into the semiconductor layer, wherein the TSC structure contacts a contact pad at a first end and contacts an interconnection layer at a second end, the first end opposite the second end.

2. The 3D memory device of claim 1 , wherein the first and second directions are the same.

3. The 3D memory device of claim 1 , wherein the first and second directions are different directions.

4. The 3D memory device of claim 1 , wherein the TSC structure contacts a contact structure of the interconnect layer.

5. The 3D memory device of claim 1 , wherein the first staircase region further includes a third staircase structure including a third plurality of stairs descending in the second direction that is opposite to the first direction.

6. The 3D memory device of claim 5 , wherein a top-most stair of the first plurality of stairs is below a bottom-most stair of the third plurality of stairs.

7. The 3D memory device of claim 5 , wherein the first staircase region further includes a fourth staircase structure including a fourth plurality of stairs descending in the first direction, and wherein the third staircase structure abuts the first and fourth staircase structures.

8. The 3D memory device of claim 1 , wherein the contact region is between the first staircase region and the second staircase region.

9. The 3D memory device of claim 1 , further including a connector structure between the first and second memory arrays in the first direction or the second direction, wherein an extension direction of the connector structure is in the first direction or the second direction.

10. The 3D memory device of claim 9 , wherein the connector structure connects the first and second memory arrays.

11. The 3D memory device of claim 9 , wherein the connector structure includes pairs of control gates and dielectric layers alternatingly.

12. The 3D memory device of claim 9 , wherein at least one stair of the first plurality of stairs is electrically coupled to the first memory array or the second memory array through the connector structure.

13. The 3D memory device of claim 1 , further including:
a bonding layer above the TSC structure and the staircase structure; and
a semiconductor structure in contact with the bonding layer, wherein the semiconductor structure includes a peripheral chip.

14. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure, including:
first and second memory array structures disposed on a semiconductor layer;
a staircase structure disposed between the first and second memory array structures and including first and second staircase structures, wherein:
the first staircase structure includes a first plurality of stairs descending in a first direction; and
the second staircase structure includes a second plurality of stairs descending in a second direction;

a contact region between with the first and second staircase structures, wherein the contact region includes a through silicon contact (TSC) structure extending through an insulating layer and into the semiconductor layer, wherein the TSC structure contacts a contact pad at a first end and contacts an interconnection layer at a second end, the first end opposite the second end; and
a first bonding layer over the TSC structure; and

a second semiconductor structure, including:
a peripheral circuit; and
a second bonding layer over the peripheral circuit, wherein the second bonding layer is in contact with the first bonding layer.

15. The 3D memory device of claim 14 , wherein the first and second directions are the same.

16. The 3D memory device of claim 14 , wherein the first and second directions are different directions.

17. The 3D memory device of claim 14 , further including a third staircase structure abutting the second staircase structure, wherein the third staircase structure includes a third plurality of stairs descending in the first direction.

18. The 3D memory device of claim 17 , wherein:
the first and second staircase structures abut each other;
the contact region is in contact with the third staircase structure; and
the first and second directions are opposite to each other.

19. The 3D memory device of claim 14 , further including a connector structure between the first and second memory array structures, wherein at least one stair of the first plurality of stairs is electrically coupled to the first memory array structure or the second memory array structure through the connector structure.

20. The 3D memory device of claim 19 , wherein the connector structure includes pairs of control gates and dielectric layers alternatingly.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Wang Di
• Zhang Zhong
• Zhou Wenxi

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title