Staircase structures for three-dimensional memory device double-sided routing

Patent metadata

Field	Value
Publication number	US-10847534-B2
Application number	US-201816138994-A
Country	US
Kind code	B2
Filing date	Sep 22, 2018
Priority date	Jun 28, 2018
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

Embodiments of staircase structures for three-dimensional (3D) memory devices double-sided routing are disclosed. In an example, a 3D memory device includes a substrate, a memory stack disposed above the substrate and including conductor/dielectric layer pairs stacked alternatingly, and an array of memory strings each extending vertically through an inner region of the memory stack. An outer region of the memory stack includes a first staircase structure disposed on the substrate and a second staircase structure disposed above the first staircase structure. First edges of the conductor/dielectric layer pairs in the first staircase structure along a vertical direction away from the substrate are staggered laterally away from the array of memory strings. Second edges of the conductor/dielectric layer pairs in the second staircase structure along the vertical direction away from the substrate are staggered laterally toward the array of memory strings.

First claim

What is claimed is:

1. A three-dimensional (3D) memory device, comprising:
a substrate;
a memory stack disposed on the substrate and comprising a plurality of conductor/dielectric pairs, wherein the conductor/dielectric pairs comprise a plurality of conductor layers and dielectric layers stacked alternatingly; and
an array of memory strings each extending vertically through an inner region of the memory stack,
wherein an outer region of the memory stack comprises a first staircase structure disposed on the substrate and a second staircase structure disposed above the first staircase structure;
first edges of the plurality of conductor/dielectric layer pairs in the first staircase structure along a vertical direction away from the substrate are staggered laterally away from the array of memory strings; and
second edges of the plurality of conductor/dielectric layer pairs in the second staircase structure along the vertical direction away from the substrate are staggered laterally toward the array of memory strings.

2. The 3D memory device of claim 1 , wherein:
the outer region of the memory stack further comprises a third staircase structure disposed on the substrate and a fourth staircase structure disposed above the third staircase structure;
third edges of the plurality of conductor/dielectric layer pairs in the third staircase structure along the vertical direction away from the substrate are staggered laterally away from the array of memory strings; and
fourth edges of the plurality of conductor/dielectric layer pairs in the fourth staircase structure along the vertical direction away from the substrate are staggered laterally toward the array of memory strings.

3. The 3D memory device of claim 1 , wherein a length of each of the conductor/dielectric layer pairs decreases from a middle conductor/dielectric layer pair toward top and bottom conductor/dielectric layer pairs, respectively.

4. The 3D memory device of claim 2 , wherein a first number of the conductor/dielectric layer pairs in each of the first and third staircase structures is the same, and a second number of the conductor/dielectric layer pairs in each of the second and fourth staircase structures is the same.

5. The 3D memory device of claim 4 , wherein the first number is the same as the second number.

6. The 3D memory device of claim 1 , further comprising:
a first interconnect layer disposed below the memory stack; and
a plurality of first via contacts each in contact with a conductor layer in one of the conductor/dielectric layer pairs in the first staircase structure, the first via contacts each electrically connected to the first interconnect layer.

7. The 3D memory device of claim 6 , wherein:
the first interconnect layer and the memory stack are disposed at opposite sides of the substrate; and
the 3D memory device further comprises a plurality of second via contacts each extending through the substrate and electrically connected to the first interconnect layer and one of the first via contacts.

8. The 3D memory device of claim 1 , further comprising:
a second interconnect layer disposed above the memory stack; and
a plurality of third via contacts each in contact with a conductor layer in one of the conductor/dielectric layer pairs in the second staircase structure, the third via contacts each electrically connected to the second interconnect layer.

9. The 3D memory device of claim 1 , wherein:
the first edges of each adjacent conductor/dielectric layer pairs in the first staircase structure are staggered laterally away from the array of memory strings, and
the second edges of each adjacent conductor/dielectric layer pairs in the second staircase structure are staggered laterally toward the array of memory strings.

10. The 3D memory device of claim 9 , wherein an offset of the first edges of each adjacent conductor/dielectric layer pairs in the first staircase structure is the same as an offset of the second edges of each adjacent conductor/dielectric layer pairs in the second staircase structure.

11. The 3D memory device of claim 1 , wherein the memory stack has a substantial hexagon shape in a side view.

12. A three-dimensional (3D) memory device, comprising:
a substrate;
a memory stack disposed on the substrate and comprising a plurality of conductor/dielectric pairs, wherein the conductor/dielectric pairs comprise a plurality of conductor layers and dielectric layers stacked alternatingly, and
a length of each conductor/dielectric layer pair decreases from a middle of the memory stack to a bottom of the memory stack, wherein the bottom of the memory stack is adjacent to the substrate; and
an array of memory strings each extending vertically through an inner region of the memory stack,
wherein an outer region of the memory stack comprises a first staircase structure disposed on the substrate and a second staircase structure disposed on the substrate;
first edges of the plurality of conductor/dielectric layer pairs in the first staircase structure along a vertical direction away from the substrate are staggered laterally away from the array of memory strings; and
second edges of the plurality of conductor/dielectric layer pairs in the second staircase structure along the vertical direction away from the substrate are staggered laterally away from the array of memory strings.

13. A three-dimensional (3D) memory device, comprising:
a substrate;
a memory stack disposed above the substrate and comprising a plurality of conductor/dielectric pairs, wherein the conductor/dielectric pairs comprise a plurality of conductor layers and dielectric layers stacked alternatingly, and wherein a length of each of the conductor/dielectric layer pairs decreases from a middle conductor/dielectric layer pair toward a top conductor/dielectric layer pair and a bottom conductor/dielectric layer pair, respectively; and
an array of memory strings each extending vertically through the memory stack.

14. The 3D memory device of claim 13 , further comprising:
a first interconnect layer disposed above the memory stack; and
a plurality of first via contacts in contact with the conductor layers in some of the conductor/dielectric layer pairs, respectively, the first via contacts electrically connected to the first interconnect layer.

15. The 3D memory device of claim 13 , further comprising:
a second interconnect layer disposed below the memory stack; and
a plurality of second via contacts in contact with the conductor layers in some of the conductor/dielectric layer pairs, respectively, the second via contacts electrically connected to the second interconnect layer.

16. The 3D memory device of claim 15 , wherein:
the second interconnect layer and the memory stack are disposed at opposite sides of the substrate; and
the 3D memory device further comprises a plurality of third via contacts extending through the substrate and electrically connected to the second interconnect layer and the second via contacts.

17. The 3D memory device of claim 13 , wherein:
first edges of one side of each adjacent conductor/dielectric layer pairs are staggered laterally; and
second edges on another side of each adjacent conductor/dielectric layer pairs are staggered laterally.

18. The 3D memory device of claim 17 , wherein:
a first offset of the first edges of each adjacent conductor/dielectric layer pairs is the same; and
a second offset of the second edges of each adjacent conductor/dielectric layer pairs is the same.

19. The 3D memory device of claim 18

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Chu Shao-Fu Sanford

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L23/528

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L23/5226

  Electricity · mapped topic