Field effect transistors with gate fins and method of making the same

Patent metadata

Field	Value
Publication number	US-12279445-B2
Application number	US-202117562635-A
Country	US
Kind code	B2
Filing date	Dec 27, 2021
Priority date	Sep 14, 2021
Publication date	Apr 15, 2025
Grant date	Apr 15, 2025

Abstract

A semiconductor structure includes a semiconductor substrate containing a shallow trench isolation structure that laterally surrounds a transistor active region, at least one line trench vertically extending into the semiconductor substrate, and a source region and a drain region located in the transistor active region. A contoured channel region continuously extends from the source region to the drain region underneath the at least one line trench. A gate dielectric contacts all surfaces of the at least one line trench and extends over an entirety of the contoured channel region. A gate electrode containing at least one fin portion overlies the gate dielectric.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a semiconductor substrate containing a shallow trench isolation structure that laterally surrounds a transistor active region that is a portion of the semiconductor substrate; and
a field effect transistor comprising:
at least one line trench vertically extending from a planar top surface of the transistor active region into the semiconductor substrate;
a channel region comprising a portion of the transistor active region that laterally surrounds or underlies the at least one line trench;
a gate dielectric contacting all surfaces of the at least one line trench and comprising a planar gate dielectric portion that extends over a top surface of the channel region;
a gate electrode comprising a planar gate electrode portion that overlies the planar gate dielectric portion and at least one gate electrode fin portion located within the at least one line trench; and
a source region and a drain region located in the transistor active region and laterally spaced from each other by the channel region;
wherein:
the channel region comprises a contoured channel region which continuously extends from the source region to the drain region underneath the planar top surface of the transistor active region and underneath the at least one line trench;
the at least one line trench extends along a first horizontal direction;
the source region is separated from the drain region along a second horizontal direction which is perpendicular to the first horizontal direction;
the shallow trench isolation structure comprises a pair of first shallow trench isolation structure walls that laterally extend along the first horizontal direction and contacting the transistor active region and a pair of second shallow trench isolation structure walls that laterally extend along the second horizontal direction and adjoined to the pair of first shallow trench isolation structure walls and contacting the transistor active region;
the least one line trench laterally extends along the first horizontal direction from one of the second shallow trench isolation structure walls to another one of the second shallow trench isolation structure walls;
sidewalls of the at least one line trench are parallel to the first horizontal direction and perpendicular to the second horizontal direction;
the pair of second shallow trench isolation structure walls is tapered relative to a vertical plane laterally extending along the second horizontal direction;
boundaries of each of the at least one line trench comprise segments of the pair of second shallow trench isolation structure walls; and
the at least one line trench has a greater width along the first horizontal direction at a first horizontal plane including of a bottom surface of the shallow trench isolation structure than at a second horizontal plane including a top surface of the shallow trench isolation structure.

2. A semiconductor structure, comprising:
a semiconductor substrate containing a shallow trench isolation structure that laterally surrounds a transistor active region that is a portion of the semiconductor substrate; and
a field effect transistor comprising:
at least one line trench vertically extending from a planar top surface of the transistor active region into the semiconductor substrate;
a channel region comprising a portion of the transistor active region that laterally surrounds or underlies the at least one line trench;
a gate dielectric contacting all surfaces of the at least one line trench and comprising a planar gate dielectric portion that extends over a top surface of the channel region;
a gate electrode comprising a planar gate electrode portion that overlies the planar gate dielectric portion and at least one gate electrode fin portion located within the at least one line trench; and
a source region and a drain region located in the transistor active region and laterally spaced from each other by the channel region;
wherein:
the channel region comprises a contoured channel region which continuously extends from the source region to the drain region underneath the planar top surface of the transistor active region and underneath the at least one line trench;
the at least one line trench extends along a first horizontal direction;
the source region is separated from the drain region along a second horizontal direction which is perpendicular to the first horizontal direction;
the shallow trench isolation structure comprises a pair of first shallow trench isolation structure walls that laterally extend along the first horizontal direction and contacting the transistor active region and a pair of second shallow trench isolation structure walls that laterally extend along the second horizontal direction and adjoined to the pair of first shallow trench isolation structure walls and contacting the transistor active region;
the least one line trench laterally extends along the first horizontal direction from one of the second shallow trench isolation structure walls to another one of the second shallow trench isolation structure walls;
sidewalls of the at least one line trench are parallel to the first horizontal direction and perpendicular to the second horizontal direction; and
the gate dielectric contacts the pair of second shallow trench isolation structure walls continuously between a first horizontal plane including of a bottom surface of the shallow trench isolation structure and a second horizontal plane including a top surface of the shallow trench isolation structure.

Assignees

• Sandisk Technologies Llc
• Sandisk Technologies Inc

Inventors

• Pulugurtha Srinivas
• Zhang Yanli
• Alsmeier Johann
• Togo Mitsuhiro

Classifications

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/601

  having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  (lightly doped source or drain extensions for TFTs H10D30/6715) · CPC title

• H10D30/0227

  having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET · CPC title