Modular construction of hybrid-bonded semiconductor die assemblies and related systems and methods

Patent metadata

Field	Value
Publication number	US-12278202-B2
Application number	US-202217830224-A
Country	US
Kind code	B2
Filing date	Jun 1, 2022
Priority date	Jun 1, 2022
Publication date	Apr 15, 2025
Grant date	Apr 15, 2025

Abstract

Stacked semiconductor assemblies, and related systems and methods, are disclosed herein. A representative stacked semiconductor assembly can include a lowermost die and two or more modules carried by an upper surface of the lowermost die. Each of the module(s) can include a base die and one or more upper dies and/or an uppermost die carried by the base die. Each of the dies in the module is coupled via hybrid bonds between adjacent dies. Further, the base die in a lowermost module is coupled to the lowermost die by hybrid bonds. As a result of the modular construction, the lowermost die can have a first longitudinal footprint, the base die in each of the module(s) can have a second longitudinal footprint smaller than the first longitudinal footprint, and each of the upper die(s) and/or the uppermost die can have a third longitudinal footprint smaller than the second longitudinal footprint.

First claim

We claim:

1. A semiconductor die assembly, comprising:
a lowermost semiconductor die having an upper surface and a first longitudinal footprint; and
two or more modules carried by the upper surface of the lowermost semiconductor die including at least a first module stacked on the lowermost die and a second module stacked on the first module, each of the two or more modules including:
a base semiconductor die having a second longitudinal footprint smaller than the first longitudinal footprint; and
one or more upper semiconductor dies having a third longitudinal footprint smaller than the second longitudinal footprint,
wherein the one or more upper semiconductor dies and the base semiconductor die are mechanically coupled via dielectric-dielectric bonds and electrically coupled via metal-metal bonds between adjacent ones of the one or more upper semiconductor dies and the base semiconductor die, and wherein the first module and the base semiconductor die in the second module are mechanically coupled via dielectric-dielectric bonds and electrically coupled via metal-metal bonds.

2. The semiconductor die assembly of claim 1 wherein each of the two or more modules further includes a first encapsulant contained within the second longitudinal footprint and insulating sidewalls of each of the one or more upper semiconductor dies, and wherein the semiconductor die assembly further comprises a second encapsulant contained within the first longitudinal footprint and insulating sidewalls of each of the two or more modules.

3. The semiconductor die assembly of claim 1 wherein the lowermost die and the first module are mechanically coupled via dielectric-dielectric bonds and electrically coupled via metal-metal bonds between the lowermost die and the first module.

4. The semiconductor die assembly of claim 3 wherein an uppermost module of the two or more modules further includes a top semiconductor die carried by the one or more upper semiconductor dies, and wherein the top semiconductor die has a thickness configured to match an overall height of the semiconductor die assembly to a predetermined height.

5. The semiconductor die assembly of claim 1 wherein:
the base semiconductor die includes an upper surface, a lower surface opposite the upper surface, a first bond pad at the upper surface, and a through substrate via extending between the first bond pad and the lower surface; and
the one or more upper semiconductor dies include a first semiconductor die carried by the base semiconductor die, wherein the first semiconductor die includes a lower surface and a second bond pad at the lower surface of the first semiconductor die, and wherein the second bond pad is electrically coupled to the first bond pad via a metal-metal bond.

6. The semiconductor die assembly of claim 5 wherein:
the through substrate via in the base semiconductor die is a first through substrate via and the metal-metal bond is a first metal-metal bond;
the first semiconductor die includes an upper surface, a third bond pad at the upper surface of the first semiconductor die, and a second through substrate via extending between the second and third bond pads; and
the one or more upper semiconductor dies further include a second semiconductor die carried by the first semiconductor die, wherein the second semiconductor die includes a lower surface and a fourth bond pad at the lower surface of the second semiconductor die, and wherein the fourth bond pad is electrically coupled to the third bond pad via a second metal-metal bond to establish an electrical connection between the second semiconductor die and the base semiconductor die.

7. The semiconductor die assembly of claim 1 wherein each of the one or more upper semiconductor dies and the base semiconductor die includes a plurality of electrical bond pads and a plurality of thermal bond pads.

8. A semiconductor device, comprising:
a lowermost die having a first longitudinal footprint and an upper surface;
a first sub-stack of two or more dies carried by the upper surface of the lowermost die, wherein the two or more dies in the first sub-stack include a base die with a second longitudinal footprint smaller than the first longitudinal footprint and an upper die carried by the base die with a third longitudinal footprint smaller than the second longitudinal footprint, and wherein each of the two or more dies in the first sub-stack are coupled by hybrid bonds; and
a second sub-stack of two or more dies carried by the first sub-stack, wherein the two or more dies in the second sub-stack include a base die with the second longitudinal footprint and an upper die carried by the base die with the third longitudinal footprint, and wherein each of the two or more dies in the first sub-stack are coupled by hybrid bonds,
wherein the first sub-stack and the second sub-stack are coupled by hybrid bonds between the upper die in the first sub-stack and the base die in the second sub-stack.

9. The semiconductor device of claim 8 wherein:
the lowermost die includes an upper surface and a plurality of first bond pads on the upper surface; and
the base die in the first sub-stack has a lower surface and a plurality of second bond pads on the lower surface, wherein the plurality of second bond pads are individually electrically coupled to the plurality of first bond pads via a metal-metal bond.

10. The semiconductor device of claim 8 wherein:
The upper die in the first sub-stack includes an upper surface and a first bond pad on the upper surface; and
the base die in the second sub-stack has a lower surface and a second bond pad on the lower surface, wherein the hybrid bond between the upper die in the first sub-stack and the base die in the second sub-stack includes a metal-metal bond between the first bond pad and the second bond pad.

11. The semiconductor device of claim 8 wherein the lowermost die includes a first surface, a second surface opposite the first surface, at least one interconnect extending between the first surface to the second surface, and at least one bonding feature at the second surface and electrically coupled to the at least one interconnect.

12. The semiconductor device of claim 8 , further comprising an uppermost die carried by the second sub-stack, wherein the uppermost die has a fourth longitudinal footprint smaller than the second longitudinal footprint.

13. The semiconductor device of claim 8 wherein the lowermost die includes a first surface carrying the first and second sub-stacks and a second surface opposite the first surface, wherein the second surface includes a redistribution layer electrically coupled to a plurality of interconnect structures.

14. The semiconductor device of claim 8 wherein:
the first sub-stack further includes a first encapsulant within the second longitudinal footprint and at least partially surrounding the upper die of the first sub-stack;
the second sub-stack further includes a second encapsulant within the second longitudinal footprint and at least partially surrounding the upper die of the second sub-stack; and
the semiconductor device further comprises a third encapsulant within the first longitudinal footprint and at least partially surrounding the first sub-stack and the second sub-stack.

15. A method of manufacturing a semiconductor die assembly, the method comprising:
constructing two or more modules of dies, wherein constructing each of the two or more modules includes:
stacking one or more upper dies on a base die in a position to form direct contact between bond pads on a first die of the one or more upper dies and the base die and direc

Assignees

• Micron Technology Inc

Inventors

• Bhushan Bharat
• Singh Akshay N
• Street Bret K
• Datta Debjit
• Nakano Eiichi

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title