Auto-referenced memory cell read techniques

Patent metadata

Field	Value
Publication number	US-12277969-B2
Application number	US-202418661300-A
Country	US
Kind code	B2
Filing date	May 10, 2024
Priority date	Dec 22, 2017
Publication date	Apr 15, 2025
Grant date	Apr 15, 2025

Abstract

Methods, systems, and devices related to auto-referenced memory cell read techniques are described. The auto-referenced read may encode user data to include a predetermined number of bits having a first logic state prior to storing the user data in memory cells. The auto-referenced read may store a total number of bits of the user data having a first logic state in a separate set of memory cells. Subsequently, reading the user data may be carried out by applying a read voltage to the memory cells storing the user data while monitoring a series of switching events by activating a subset of the memory cells having the first logic state. During the read operation, the auto-referenced read may compare the number of activated memory cells to either the predetermined number or the total number to determine whether all the bits having the first logic state has been detected. When the number of activated memory cells matches either the predetermined number or the total number, the auto-referenced read may determine that the memory cells that have been activated correspond to the first logic state.

First claim

What is claimed is:

1. A method, comprising:
applying a first read voltage to a first set of memory cells and a second read voltage to a second set of memory cells;
updating a first counter based at least in part on applying the first read voltage to the first set of memory cells;
updating a second counter based at least in part on applying the second read voltage to the second set of memory cells; and
reading the first set of memory cells based at least in part on updating the first counter and the second counter.

2. The method of claim 1 , wherein the second set of memory cells stores a count value, the count value indicative of a quantity of memory cells within the first set of memory cells that store a first logic value.

3. The method of claim 1 , wherein:
updating the first counter comprises incrementing the first counter in response to each memory cell that is activated within the first set of memory cells while the first read voltage is applied to the first set of memory cells; and
updating the second counter comprises incrementing the second counter in response to each memory cell that is activated within the second set of memory cells while the second read voltage is applied to the second set of memory cells.

4. The method of claim 1 , wherein reading the first set of memory cells based at least in part on updating the first counter and the second counter comprises:
determining a count value stored by the second set of memory cells based at least in part on the second counter equaling a threshold, the count value indicative of a quantity of memory cells within the first set of memory cells that store a first logic value; and
identifying one or more activated memory cells within the first set of memory cells based at least in part on a value of the first counter equaling the count value stored by the second set of memory cells, wherein the one or more activated memory cells store the first logic value.

5. The method of claim 4 , wherein reading the first set of memory cells based at least in part on updating the first counter and the second counter further comprises:
identifying one or more unactivated memory cells within the first set of memory cells based at least in part on the value of the first counter equaling the count value stored by the second set of memory cells, wherein the one or more unactivated memory cells store a second logic value.

6. The method of claim 4 , wherein the threshold is based at least in part on a quantity of memory cells included in the second set of memory cells.

7. The method of claim 4 , wherein the threshold is equal to half of the quantity of memory cells included in the second set of memory cells.

8. The method of claim 4 , further comprising:
identifying activated memory cells within the second set of memory cells based at least in part on a value of the second counter equaling the threshold, wherein activated memory cells within the second set of memory cells store the first logic value; and
determining the count value based at least in part on the activated memory cells within the second set of memory cells.

9. The method of claim 1 , further comprising:
ceasing to apply the second read voltage to the second set of memory cells based at least in part on the second counter reaching a threshold; and
ceasing to apply the first read voltage to the first set of memory cells based at least in part on the first counter reaching a count value stored by the second set of memory cells.

10. The method of claim 1 , wherein:
the first read voltage and the second read voltage are monotonically increasing.

11. The method of claim 1 , wherein the second read voltage has a different ramp rate than the first read voltage.

12. The method of claim 1 , wherein the second read voltage is offset in time relative to the first read voltage.

13. The method of claim 1 , wherein the first read voltage and the second read voltage are a same single read voltage.

14. The method of claim 1 , wherein the first set of memory cells and the second set of memory cells are coupled with a same access line.

15. An apparatus, comprising:
a memory array that comprises a first set of memory cells and a second set of memory cells; and
processing circuitry coupled with the memory array and configured to cause the apparatus to:
apply a first read voltage to the first set of memory cells and a second read voltage to the second set of memory cells;
update a first counter based at least in part on applying the first read voltage to the first set of memory cells;
update a second counter based at least in part on applying the second read voltage to the second set of memory cells; and
read the first set of memory cells based at least in part on updating the first counter and the second counter.

16. The apparatus of claim 15 , wherein:
to update the first counter, the processing circuitry is configured to cause the apparatus to increment the first counter in response to each memory cell that is activated within the first set of memory cells while the first read voltage is applied to the first set of memory cells; and
to update the second counter, the processing circuitry is configured to cause the apparatus to increment the second counter in response to each memory cell that is activated within the second set of memory cells while the second read voltage is applied to the second set of memory cells.

17. The apparatus of claim 16 , wherein, to read the first set of memory cells based at least in part on updating the first counter and the second counter, the processing circuitry is configured to cause the apparatus to:
determine a count value stored by the second set of memory cells based at least in part on the second counter equaling a threshold, the count value indicative of a quantity of memory cells within the first set of memory cells that store a first logic value; and
identify one or more activated memory cells within the first set of memory cells based at least in part on a value of the first counter equaling the count value stored by the second set of memory cells, the one or more activated memory cells associated with the first logic value.

18. The apparatus of claim 17 , wherein, to read the first set of memory cells based at least in part on updating the first counter and the second counter, the processing circuitry is further configured to cause the apparatus to:
identify one or more unactivated memory cells within the first set of memory cells based at least in part on the value of the first counter equaling the count value stored by the second set of memory cells, the one or more unactivated memory cells associated with a second logic value.

19. The apparatus of claim 17 , wherein the threshold is based at least in part on a quantity of memory cells included in the second set of memory cells.

20. The apparatus of claim 17 , wherein the threshold is based at least in part on a quantity of memory cells included in the second set of memory cells.

Assignees

• Micron Technology Inc

Inventors

• Mirichigni Graziano
• Amato Paolo
• Pio Federico
• Orlando Alessandro
• Sforzin Marco

Classifications

• H10N70/231

  based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect · CPC title

• H10B63/84

  arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C13/003

  Cell access · CPC title

• G11C7/06

  Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} · CPC title