Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2016071601-A1
Application number	US-201514841459-A
Country	US
Kind code	A1
Filing date	Aug 31, 2015
Priority date	Sep 4, 2014
Publication date	Mar 10, 2016
Grant date	—

Abstract

A semiconductor memory device includes: a memory cell array including memory strings, one of the memory strings including memory cells; word lines commonly connected to the memory strings; and a controller configured to execute a write operation and a read operation on a page, the page being stored in memory cells connected to one of the word lines. The controller is configured to measure a cell current flowing in the memory string, and adjust a write voltage applied to a word line, based on a result of the cell current.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a memory cell array including memory strings, one of the memory strings including memory cells; word lines commonly connected to the memory strings; and a controller configured to execute a write operation and a read operation on a page, the page being stored in memory cells connected to one of the word lines, wherein the controller is configured to measure a cell current flowing in the memory string, and adjust a write voltage applied to a word line, based on a measurement result of the cell current.

2 . The device of claim 1 , wherein the controller is configured to
write the measurement result the measurement result to a redundancy area of the page, read the measurement result from the redundancy area in first read, and adjust, in second read, a read voltage applied to the word line, based on the measurement result.

3 . The device of claim 1 , wherein the controller is configured to
write the measurement result in a redundancy area of the page in first write, read the measurement result from the redundancy area in second write, and adjust, in the second write, a write voltage applied to the word line, based on the measurement result.

4 . The device of claim 3 , wherein the write voltage is set to become smaller as the cell current becomes smaller.

5 . The device of claim 3 , wherein in an erase operation, the controller is configured to
read the measurement result from the redundancy area, and adjust an erase voltage, based on the measurement result.

6 . The device of claim 5 , wherein the erase voltage is set to become larger as the cell current becomes smaller.

7 . The device of claim 1 , further comprising a register configured to store parameters including information of the write voltage,
wherein the controller is configured to select one of the parameters, based on the measurement result, and determine the write voltage by using the selected parameter.

8 . The device of claim 1 , wherein the memory cells are stacked and comprise a first group and a second group which are divided along a direction of the stacking, and
the controller is configured to further adjust the write voltage in accordance with the first group and the second group.

9 . A semiconductor memory device comprising:
a memory cell array including memory strings, one of the memory strings including memory cells; word lines commonly connected to the memory strings; and a controller configured to execute a write operation and a read operation on a page, the page being stored in memory cells connected to one of the word lines, wherein the controller is configured to count a bit number of a first level which is to be written to a sampling area, which is a part of the page, to obtain a first count value, and write the first count value to a redundancy area of the page, read, in first read, the first count value from the redundancy area, and count a bit number of the first level which was read from the sampling area, and adjust, in second read, a read voltage applied to a word line, based on a difference between the first count value and a second count value by the first read.

10 . The device of claim 9 , further comprising:
a first data cache configured to store read data by the first read; and a second data cache configured to store read data by the second read, wherein the controller is configured to output either the data of the first data cache or the data of the second data cache in accordance with a command received from an outside.

11 . The device of claim 9 , further comprising:
a first data cache configured to store read data by the first read; and a second data cache configured to store read data by the second read, wherein the controller is configured to output the data of the first data cache at a first timing, and output the data of the second data cache when a command is received from an outside at a second timing.

12 . The device of claim 9 , further comprising a data cache configured to store write data received from an outside,
wherein the controller is configured to count the bit number of the first level by using the write data stored in the data cache.

13 . The device of claim 9 , further comprising a register configured to store parameters including information of the read voltage,
wherein the controller is configured to select one of the parameters, based on the difference the first count value and a second count value by the first read, and determine the read voltage by using the selected parameter.

14 . The device of claim 9 , wherein the controller is configured to set a read voltage in the second read to be higher than a read voltage in the first read.

15 . The device of claim 9 , wherein the controller is configured to step up the read voltage and repeat the read operation, when the difference between the first count value and a second count value by the first read is greater than a threshold.

Assignees

• Toshiba Kk

Inventors

• Shirakawa Masanobu
• Futatsuyama Takuya
• Abe Kenichi

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C2029/1202

  Word line control · CPC title