Delta-sigma modulator

Patent metadata

Field	Value
Publication number	US-12273128-B2
Application number	US-202318185026-A
Country	US
Kind code	B2
Filing date	Mar 16, 2023
Priority date	Mar 17, 2022
Publication date	Apr 8, 2025
Grant date	Apr 8, 2025

Abstract

A delta-sigma modulator is provided. The delta-sigma modulator includes a multiplexer, a modulation circuit and a demultiplexer. The multiplexer is configured to receive a first analog signal and a second analog signal, and output an input signal. The first analog signal and the second analog signal are in different electrical forms, and the multiplexer is configured to select, in a time-division manner, the first analog signal or the second analog signal as the input signal SIN to be output. The modulation circuit is configured to modulate the input signal into a digital signal. The demultiplexer has a first output terminal and a second output terminal, and selects the first output terminal or the second output terminal in a time-division manner to output the digital signal.

First claim

What is claimed is:

1. A delta-sigma modulator, comprising:
a multiplexer configured to receive a first analog signal and a second analog signal, and output an input signal, wherein the first analog signal and the second analog signal are in different electrical forms, and the multiplexer is configured to select, in a time-division manner, the first analog signal or the second analog signal as the input signal to be output;
a modulation circuit coupled to the multiplexer, wherein the modulation circuit is configured to modulate the input signal into a digital signal; and
a demultiplexer coupled to the modulation circuit, wherein the demultiplexer has a first output terminal and a second output terminal, and is configured to receive the digital signal and select the first output terminal or the second output terminal in the time-division manner, so as to output the digital signal;
wherein, in response to the input signal being a direct current signal, a loop filter of the modulation circuit is reset according to a reset signal with a high level, and an oversampling rate is used as a period where the reset signal changes from a low level to the high level.

2. The delta-sigma modulator according to claim 1 , wherein the modulation circuit includes:
an operation circuit configured to receive the input signal and an analog feedback signal, and calculate a difference between the input signal and the analog feedback signal to output a difference signal;
the loop filter coupled to the operation circuit, wherein the loop filter is configured to process the difference signal to generate a filtered signal;
a quantizer coupled to the loop filter, wherein the quantizer is configured to quantize the filtered signal into the digital signal; and
a digital-to-analog converter (DAC) coupled to the quantizer and the operation circuit, wherein the DAC is configured to perform a digital-to-analog conversion on the digital signal to generate the analog feedback signal.

3. The delta-sigma modulator according to claim 2 , wherein the first analog signal is the direct current (DC) signal, and the second analog signal is an alternating current (AC) signal.

4. The delta-sigma modulator according to claim 1 , further comprising:
a counter coupled to the first output terminal of the demultiplexer, wherein the counter is configured to count the digital signal outputted by the first output terminal, so as to generate a first output signal; and
a decimation filter coupled to the second output terminal of the demultiplexer, wherein the decimation filter is configured to extract the digital signal outputted from the second output terminal to generate a second output signal.

5. The delta-sigma modulator according to claim 4 , wherein the counter is reset to zero according to the reset signal.

6. The delta-sigma modulator according to claim 1 , wherein the loop filter includes a continuous-time integrator or a discrete-time integrator for integrating the difference signal, and the filtered signal is determined by an integration result outputted by the continuous-time integrator or the discrete time integrator.

7. The delta-sigma modulator according to claim 6 , wherein the continuous-time integrator includes:
a differential amplifier;
a first resistor coupled between the operation circuit and an inverting input terminal of the differential amplifier;
a second resistor coupled between the operation circuit and a non-inverting input terminal of the differential amplifier;
a first capacitor coupled between the inverting input terminal and a non-inverting output terminal of the differential amplifier; and
a second capacitor coupled between the non-inverting input terminal and an inverting output terminal of the differential amplifier.

8. The delta-sigma modulator according to claim 7 , wherein the continuous-time integrator further includes:
a first reset switch connected in parallel with the first capacitor between the inverting input terminal and the non-inverting output terminal of the differential amplifier; and
a second reset switch connected in parallel with the second capacitor between the non-inverting input terminal and the inverting output terminal of the differential amplifier;
wherein the reset signal is used to control the first reset switch and the second reset switch.

9. The delta-sigma modulator according to claim 7 , wherein the continuous-time integrator further includes:
a first reset switch coupled between a first node and a second node, the reset signal being used to control the first reset switch, wherein a first terminal of the first capacitor is coupled to the non-inverting output terminal of the differential amplifier through the first node, and a first terminal of the second capacitor is coupled to the inverting output terminal of the differential amplifier through the second node.

10. The delta-sigma modulator according to claim 7 , wherein a first terminal of the first capacitor is coupled to the non-inverting output terminal of the differential amplifier through a first node, and a first terminal of the second capacitor is coupled to the inverting output terminal of the differential amplifier through a second node, and the continuous-time integrator further includes:
a first setting switch coupled between the first node and a third node, wherein the reset signal being inverted is used to control the first setting switch, and when the loop filter is not reset, the first setting switch is controlled to couple the third node to the first node;
a first reset switch coupled between the first node and a fourth node, the reset signal being used to control the first reset switch, wherein, when the loop filter is reset, the first reset switch is controlled to couple the fourth node to the first node;
a second setting switch coupled between the second node and the fourth node, wherein the reset signal being inverted is used to control the second setting switch, and when the loop filter is not reset, the second setting switch is controlled to couple the fourth node to the second node; and
a second reset switch coupled between the second node and the third node, the reset signal being used to control the second reset switch, wherein, when the loop filter is reset, the second reset switch is controlled to couple the third node to the second node.

11. The delta-sigma modulator according to claim 6 , wherein the discrete-time integrator includes:
a differential amplifier;
a first capacitor coupled between the operation circuit and an inverting input terminal of the differential amplifier;
a second capacitor coupled between the operation circuit and a non-inverting input terminal of the differential amplifier;
a third capacitor coupled between the inverting input terminal and a non-inverting output terminal of the differential amplifier;
a fourth capacitor coupled between the non-inverting input terminal and an inverting output terminal of the differential amplifier;
a first switch coupled between the first capacitor and the operation circuit;
a second switch coupled between the second capacitor and the operation circuit;
a third switch coupled between the first capacitor and the inverting input of the differential amplifier; and
a fourth switch coupled between the second capacitor and the non-inverting input terminal of the differential amplifier, wherein the first switch and the second switch are turned on in a first time interval, and the third switch and the fourth switch are turned on in a second time interval different from the first time interval.

12. The delta-sigma modulator according to claim 11 , wherein the discrete-time integrator further includes:
a

Assignees

• Realtek Semiconductor Corp

Inventors

• Chang Chia-Ling

Classifications

• H03M3/458 Primary

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M3/462

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title

• H03M3/47 Primary

  using time-division multiplexing · CPC title