Sigma-delta analog-to-digital converter and operation method thereof

Patent metadata

Field	Value
Publication number	US-10693490-B1
Application number	US-201916529765-A
Country	US
Kind code	B1
Filing date	Aug 1, 2019
Priority date	Apr 24, 2019
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A Sigma-Delta (Σ-Δ) analog-to-digital converter (ADC) and operation method thereof are provided. The Σ-Δ ADC includes a Σ-Δ modulator, a dynamic element matching (DEM) circuit and a control circuit. An input terminal of the Σ-Δ modulator is configured to receive an analog signal. The Σ-Δ modulator is configured to convert the analog signal into a digital signal based on a feedback signal. The DEM circuit is coupled to the Σ-Δ modulator to receive the digital signal. The DEM circuit is configured to perform a DEM algorithm on the digital signal to generate a feedback signal, and provide the feedback signal to the Σ-Δ modulator. The control circuit listens to the digital signal to detect a mute period. The control circuit disables the DEM circuit during the mute period to suspend a progress of the DEM algorithm.

First claim

What is claimed is:

1. A Sigma-Delta (Σ-Δ) analog-to-digital converter, comprising:
a Σ-Δ modulator, having an input terminal for receiving an analog signal, and configured to convert the analog signal into a digital signal according to a feedback signal;
a dynamic element matching circuit, coupled to the Σ-Δ modulator to receive the digital signal, and configured to perform at least one dynamic element matching algorithm on the digital signal to generate the feedback signal, and provide the feedback signal to the Σ-Δ modulator; and
a control circuit, coupled to the Σ-Δ modulator to receive the digital signal, wherein the control circuit listens to the digital signal to detect a mute period, and the control circuit disables the dynamic element matching circuit during the mute period to suspend a progress of the at least one dynamic element matching algorithm.

2. The Σ-Δ analog-to-digital converter as claimed in claim 1 , wherein the control circuit enables the dynamic element matching circuit to restore the progress of the at least one dynamic element matching algorithm after the mute period is ended.

3. The Σ-Δ analog-to-digital converter as claimed in claim 1 , wherein the dynamic element matching circuit comprises:
a first dynamic element matching circuit, having an input terminal coupled to the Σ-Δ modulator to receive the digital signal, wherein the first dynamic element matching circuit performs a first dynamic element matching algorithm on the digital signal to generate a first feedback signal;
a second dynamic element matching circuit, having an input terminal coupled to the Σ-Δ modulator to receive the digital signal, wherein the second dynamic element matching circuit performs a second dynamic element matching algorithm different to the first dynamic element matching algorithm on the digital signal to generate a second feedback signal; and
a switching circuit, having a common terminal coupled to the Σ-Δ modulator to provide the feedback signal, wherein a first selection terminal of the switching circuit is coupled to the first dynamic element matching circuit to receive the first feedback signal, and a second selection terminal of the switching circuit is coupled to the second dynamic element matching circuit to receive the second feedback signal.

4. The Σ-Δ analog-to-digital converter as claimed in claim 3 , wherein the first dynamic element matching algorithm comprises a bit continuity algorithm, and the second dynamic element matching algorithm comprises a bit dispersion algorithm.

5. The Σ-Δ analog-to-digital converter as claimed in claim 4 , wherein the bit continuity algorithm comprises a data weighted averaging algorithm, and the bit dispersion algorithm comprises a tree structured algorithm.

6. The Σ-Δ analog-to-digital converter as claimed in claim 3 , wherein the first dynamic element matching circuit is controlled by the control circuit, and the control circuit disables the first dynamic element matching circuit during the mute period to suspend a progress of the first dynamic element matching algorithm.

7. The Σ-Δ analog-to-digital converter as claimed in claim 3 , wherein the second dynamic element matching circuit is controlled by the control circuit, and the control circuit disables the second dynamic element matching circuit during the mute period to suspend a progress of the second dynamic element matching algorithm.

8. The Σ-Δ analog-to-digital converter as claimed in claim 3 , wherein the switching circuit is controlled by the control circuit, the control circuit controls the switching circuit to dynamically select one of the first feedback signal and the second feedback signal to serve as the feedback signal during a normal operation period, and the control circuit controls the switching circuit to keep taking one of the first feedback signal and the second feedback signal to serve as the feedback signal during the mute period.

9. An operation method of a Σ-Δ analog-to-digital converter, comprising:
converting an analog signal into a digital signal by a Σ-Δ modulator according to a feedback signal;
performing at least one dynamic element matching algorithm on the digital signal by a dynamic element matching circuit to generate the feedback signal;
providing the feedback signal to the Σ-Δ modulator by the dynamic element matching circuit;
listening to the digital signal by a control circuit to detect a mute period; and
disabling the dynamic element matching circuit by the control circuit during the mute period to suspend a progress of the at least one dynamic element matching algorithm.

10. The operation method of the Σ-Δ analog-to-digital converter as claimed in claim 9 , further comprising:
enabling the dynamic element matching circuit by the control circuit to restore the progress of the at least one dynamic element matching algorithm after the mute period is ended.

11. The operation method of the Σ-Δ analog-to-digital converter as claimed in claim 9 , wherein the operation of performing the at least one dynamic element matching algorithm comprises:
performing a first dynamic element matching algorithm on the digital signal by a first dynamic element matching circuit to generate a first feedback signal;
performing a second dynamic element matching algorithm different to the first dynamic element matching algorithm on the digital signal by a second dynamic element matching circuit to generate a second feedback signal; and
dynamically selecting one of the first feedback signal and the second feedback signal to serve as the feedback signal by a switching circuit.

12. The operation method of the Σ-Δ analog-to-digital converter as claimed in claim 11 , wherein the first dynamic element matching algorithm comprises a bit continuity algorithm, and the second dynamic element matching algorithm comprises a bit dispersion algorithm.

13. The operation method of the Σ-Δ analog-to-digital converter as claimed in claim 12 , wherein the bit continuity algorithm comprises a data weighted averaging algorithm, and the bit dispersion algorithm comprises a tree structured algorithm.

14. The operation method of the Σ-Δ analog-to-digital converter as claimed in claim 11 , further comprising:
disabling the first dynamic element matching circuit by the control circuit during the mute period to suspend a progress of the first dynamic element matching algorithm.

15. The operation method of the Σ-Δ analog-to-digital converter as claimed in claim 11 , further comprising:
disabling the second dynamic element matching circuit by the control circuit during the mute period to suspend a progress of the second dynamic element matching algorithm.

16. The operation method of the Σ-Δ analog-to-digital converter as claimed in claim 11 , further comprising:
controlling the switching circuit by the control circuit to dynamically select one of the first feedback signal and the second feedback signal to serve as the feedback signal during a normal operation period; and
controlling the switching circuit by the control circuit to keep taking one of the first feedback signal and the second feedback signal to serve as the feedback signal during the mute period.

17. A Σ-Δ analog-to-digital converter, comprising:
a Σ-Δ modulator, having an input terminal for receiving an analog signal, and configured to convert the analog signal into a digital signal according to a feedback signal;
a first dynamic element matching circuit, having an input terminal coupled to the Σ-Δ modulator to receive the digital signal, wherein the first dynamic element matching circuit is configured to p

Assignees

• Faraday Tech Corp

Inventors

• Chen Chiao-Min
• Wu Min-Yuan
• Shih Shih-Yi
• Chen Po-Liang

Classifications

• H03M3/338

  by permutation in the time domain, e.g. dynamic element matching (in multiple bit sub-converters H03M1/066) · CPC title

• H03M3/32 Primary

  with special provisions or arrangements for power saving, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains, by selectively turning on stages when needed · CPC title

• H03M3/472

  Shared, i.e. using a single converter for multiple channels · CPC title

• H03M3/462

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title

• H03M1/0665 Primary

  using data dependent selection of the elements, e.g. data weighted averaging · CPC title