Multiplexed sigma-delta analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-10355709-B1
Application number	US-201816111440-A
Country	US
Kind code	B1
Filing date	Aug 24, 2018
Priority date	Aug 24, 2018
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A sigma-delta ADC circuit with an analog loop filter circuit can be multiplexed between different inputs by flushing the memory of the analog loop filter integrators and the digital decimation filter and filling it with new data for the current input. However, filling the memory can be slow with respect to the sampling frequency because the information about past history has to be built up before meaningful output data can be generated. Thus, the multiplexing rate between channels using a sigma-delta ADC circuit can be slowed by such memory flushing. A multiplexed sigma-delta ADC circuit is described that can overcome these problems so as to be able to support cycle-by-cycle sampling of multiple channels. These techniques can provide a fast sigma-delta analog-to-digital converter (ADC) circuit that is small in area and that can multiplex over a number of channels dynamically.

First claim

The claimed invention is:

1. A multiplexed multiple channel sigma-delta (SD) analog-to-digital converter (ADC) circuit comprising:
a shared analog circuit configured to receive a selected one of a plurality of analog input signals, the shared analog circuit including:
an ADC circuit coupled to an input of the analog circuit; and
a digital-to-analog converter (DAC) circuit configured to provide an analog feedback signal to the input of the analog circuit; and

a plurality of digital channels coupled to an output of the shared analog circuit and the DAC circuit, each of the plurality digital channels configured to generate a digital output signal representing a corresponding one of the analog input signals.

2. The SD ADC circuit of claim 1 , further comprising:
a gain amplifier circuit coupled to an input of the ADC circuit and configured to receive and amplify a difference between an output of the DAC circuit and one of the received analog input signals;
a first chop switch circuit coupled to an input of the gain amplifier circuit; and
a second chop switch circuit coupled to an output of the gain amplifier circuit.

3. The SD ADC circuit of claim 2 , further comprising:
a first multiplexer circuit coupled to the input of the analog circuit and configured to select the one of the plurality of analog input signals;
a second multiplexer circuit coupled to an input of the DAC circuit and each the plurality of digital channels;
a digital demultiplexer circuit coupled to an output of the analog circuit and each of the plurality of digital channels, the demultiplexer circuit configured to select one of the plurality of digital circuits to receive the output of the analog circuit; and
a controller circuit configured to:
control operation of the first and second multiplexer circuits and the demultiplexer circuit; and
control operation of the first and second chop switches.

4. The SD ADC of claim 3 , wherein the controller circuit is configured to control operation of the demultiplexer circuit to select the plurality of digital channels in a sequential pattern.

5. The SD ADC of claim 3 , wherein the controller circuit is configured to control operation of the demultiplexer circuit to select the plurality of digital channels in a non-sequential pattern.

6. The SD ADC of claim 1 , wherein the ADC circuit is a memoryless ADC circuit.

7. The SD ADC of claim 1 , wherein each of the plurality of digital channels includes:
a quantizer circuit coupled to an output of the digital filter circuit;
a digital filter circuit configured to receive an output signal of the analog circuit and output a filter circuit output signal to the DAC circuit; and
a digital decimation filter circuit configured to produce a digital output signal corresponding to a particular one of the received analog input signals.

8. The SD ADC circuit of claim 7 , wherein each digital filter circuit includes a digital integrator circuit.

9. The SD ADC of claim 7 , wherein each of the plurality of digital channels further includes:
a quantization error compensation circuit coupled to an input of the digital decimation filter and the output of the quantizer circuit, the quantization error compensation circuit configured to combine the output signal of the analog circuit with an input signal of the DAC circuit and output a quantization error-compensated signal to the digital decimation filter.

10. A method of multiplexing multiple channels using a sigma-delta (SD) analog-to-digital converter (ADC) circuit, the method comprising:
performing, using a shared analog circuit, an analog-to-digital conversion of a first input signal selected from a plurality of received analog input signals;
processing a digital output of the shared analog circuit using a first digital channel selected from a plurality of digital channels;
performing a digital-to-analog conversion on the processed digital output to generate a feedback signal to apply to an input of the shared analog circuit; and
generating a digital output signal representing a corresponding one of the analog input signals.

11. The method of claim 10 , further comprising:
receiving and amplifying a difference between the feedback signal and one of the received analog input signals;
controlling chop switch circuits coupled to an input and an output of the gain amplifier circuit; and
controlling a first multiplexer circuit to select the first one of the plurality of the received analog input signals; and
controlling a second multiplexer circuit to select one of the plurality of digital channels to couple to an input of a digital-to-analog converter (DAC) circuit.

12. The method of claim 10 , further comprising:
selecting other ones of the plurality of digital channels in a sequential pattern to receive a digital output of the shared analog circuit.

13. The method of claim 10 , further comprising:
selecting other ones of the plurality of digital channels in a non-sequential pattern to receive a digital output of the shared analog circuit.

14. The method of claim 10 , wherein performing, using a shared analog circuit, an analog-to-digital conversion of a first input signal selected from a plurality of received analog input signals includes:
performing an analog-to-digital conversion on the selected first input signal using a memoryless ADC circuit.

15. The method of claim 10 , wherein performing, using a shared analog circuit, an analog-to-digital conversion of a first input signal selected from a plurality of received analog input signals includes:
performing a successive approximation register (SAR) ADC operation on the selected first input signal.

16. The method of claim 10 , wherein performing, using the shared analog circuit, the analog-to-digital conversion of the selected first input signal includes:
performing a flash ADC operation on the selected first input signal.

17. The method of claim 10 , wherein performing, using the shared analog circuit, the analog-to-digital conversion of the selected first input signal includes:
performing a pipelined ADC operation on the selected first input signal.

18. The method of claim 10 , further comprising:
combining the digital output signal of the analog circuit with an input signal of a digital-to-analog converter (DAC) circuit and outputting a quantization error-compensated signal to a digital decimation filter.

19. A multiplexed multiple channel sigma-delta (SD) analog-to-digital converter (ADC) circuit comprising:
means for performing, using a shared analog circuit, an analog-to-digital conversion of a first input signal selected from a plurality of received analog input signals;
means for processing the digital output of the shared analog circuit using a first digital channel selected from a plurality of digital channels;
means for performing a digital-to-analog conversion on the processed digital output to generate a feedback signal to apply to an input of the shared analog circuit; and
means for generating a digital output signal representing a corresponding one of the analog input signals.

20. The SD ADC circuit of claim 18 , further comprising:
means for receiving and amplifying a difference between the feedback signal and one of the received analog input signals;
means for chopping an input and an output of the gain amplifier circuit; and
means for selecting the first one of the plurality of the received analog input signals; and
means for selecting one of the plurality of digital channels to couple to an input of

Assignees

• Analog Devices Inc

Inventors

• Sharma Yogesh Jayaraman
• Kalb Arthur J

Classifications

• H03M3/496

  Details of sampling arrangements or methods · CPC title

• H03M3/422

  having one quantiser only · CPC title

• H03M3/472 Primary

  Shared, i.e. using a single converter for multiple channels · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/474 Primary

  using time-division multiplexing · CPC title