Integrated photonics and processor package with redistribution layer and EMIB connector

Patent metadata

Field	Value
Publication number	US-12266608-B2
Application number	US-202017104963-A
Country	US
Kind code	B2
Filing date	Nov 25, 2020
Priority date	Jun 25, 2020
Publication date	Apr 1, 2025
Grant date	Apr 1, 2025

Abstract

Embodiments described herein may be related to apparatuses, processes, and techniques related to packages that include CPUs and PICs electrically coupled via an interconnect bridge. In embodiments, the PIC are electrically coupled with the EMIB using a fan out RDL to extend reach of the PIC electrical connectors. EICs may be electrically coupled between the PIC and the interconnect bridge. The CPUs may be CPUS, graphical processing units (GPUs), field programmable gate arrays (FPGAs), or other processors. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. A package comprising:
a substrate;
an interconnect bridge on the substrate;
a redistribution layer (RDL) having a top side and a bottom side opposite the top side, wherein the bottom side of the RDL is on the interconnect bridge and electrically coupled with the interconnect bridge;
a photonic integrated circuit (PIC) coupled to the top side of the RDL, wherein the PIC is electrically coupled with the interconnect bridge;
an electrical integrated circuit (EIC) that is electrically coupled with the RDL, the PIC, and the interconnect bridge, wherein the EIC is vertically intervening between the PIC and the RDL; and
a processing unit on the interconnect bridge, wherein the PIC and the processing unit are electrically coupled through the RDL and the interconnect bridge.

2. The package of claim 1 , wherein an electrical connection on the bottom side of the RDL is electrically coupled with the PIC and wherein the electrical connection is outside a footprint of the PIC.

3. The package of claim 1 , wherein the processing unit is two or more processing units.

4. The package of claim 1 , wherein the processing unit is a selected one of: a CPU, a GPU, an FPGA, or other specialized processor; and wherein the interconnect bridge is an embedded multi-die interconnect bridge (EMIB).

5. The package of claim 1 , wherein the EIC further includes a selected one or more of: a trans-impedance amplifier (TIA), a clock data recovery circuit (CDR), or a driver.

6. The package of claim 1 , wherein the EIC includes a selected one or more of: a through silicon via (TSV) or a copper pillar.

7. The package of claim 1 , wherein the EIC is two or more EICs.

8. The package of claim 1 , wherein the RDL is a fan out RDL.

9. The package of claim 1 , wherein the PIC is two or more PICS.

10. The package of claim 1 , further comprising another die physically and electrically coupled with the RDL.

11. A system comprising:
a package comprising:
a substrate;
an interconnect bridge on the substrate;
a redistribution layer (RDL) having a top side and a bottom side opposite the top side, wherein the bottom side of the RDL is on the interconnect bridge and electrically coupled with the interconnect bridge;
a photonic integrated circuit (PIC) coupled to the top side of the RDL, wherein the PIC is electrically coupled with the interconnect bridge;
a central processing unit on the interconnect bridge, wherein the PIC and the central processing unit are electrically coupled through the RDL and the interconnect bridge, wherein an electrical connection on the bottom side of the RDL is electrically coupled with the PIC and wherein the electrical connection is outside a footprint of the PIC in relation to the RDL; and
an electrical integrated circuit (EIC) electrically coupled with the RDL, the PIC, and the interconnect bridge, wherein the EIC is vertically intervening between the PIC and the RDL; and
a fiber-optic cable optically coupled with a portion of the PIC extending laterally beyond the RDL.

12. The system of claim 11 , the package further comprising an integrated heat spreader (IHS) thermally coupled with the PIC or thermally coupled with the central processing unit.

Assignees

• Intel Corp

Inventors

• Jadhav Susheel
• Brown Kenneth
• Hui David
• Liao Ling
• Islam Syed S

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W72/019

  of bond pads · CPC title

• H10W70/652

  Cross-sectional shapes · CPC title

• H10W70/655

  Fan-out layouts · CPC title