Conductive base embedded interconnect

Patent metadata

Field	Value
Publication number	US-10535595-B2
Application number	US-201515776402-A
Country	US
Kind code	B2
Filing date	Dec 26, 2015
Priority date	Dec 26, 2015
Publication date	Jan 14, 2020
Grant date	Jan 14, 2020

Abstract

Embodiments are generally directed to a conductive base embedded interconnect. An embodiment of an apparatus includes a substrate; an embedded interconnect layer in a first side of the substrate, the embedded interconnect layer including a plurality of contacts; and one or more conductive paths through the substrate, the one or more conductive paths being connected with the embedded interconnect layers.

First claim

What is claimed is:

1. An apparatus comprising:
a substrate, wherein the substrate comprises a silicon substrate;
an embedded interconnect layer in a first side of the substrate, the embedded interconnect layer including a plurality of contacts;
one or more conductive paths through the substrate, the one or more conductive paths being connected with the embedded interconnect layer, and the one or more conductive paths including a plurality of through silicon vias, the embedded interconnect layer being coupled to a first end of the plurality of through silicon vias;
a redistribution layer coupled with a second end of the plurality of through silicon vias at a second side of the substrate; and
an organic substrate having a wire layer coupled to the redistribution layer using a conductive adhesive.

2. The apparatus of claim 1 , wherein the conductive adhesive is an anisotropic conductive adhesive, wherein applying pressure to the anisotropic conductive adhesive creates an electrical connection by compression of conductive particles.

3. The apparatus of claim 1 , wherein the one or more conductive paths include a plurality of conductive paths from the wire layer of the organic substrate to the embedded interconnect layer through the through silicon vias.

4. An apparatus comprising:
a substrate;
an embedded interconnect layer in a first side of the substrate, the embedded interconnect layer including a plurality of contacts; and
one or more conductive paths through the substrate, the one or more conductive paths being connected with the embedded interconnect layers, wherein the substrate is a conductive substrate, the embedded interconnect layer having an ohmic contact with the conductive substrate, and wherein the apparatus is coupled with a wire layer of an organic substrate using a conductive adhesive applied to a second side of the conductive substrate.

5. The apparatus of claim 4 , wherein the one of more conductive paths include a single conductive path from the wire layer of the organic substrate to the embedded interconnect layer through the conductive substrate.

6. A method comprising:
providing a substrate, the substrate including a silicon substrate;
embedding metal and dielectric layers in a first side of the substrate to form an embedded interconnect layer, the embedded interconnect layer including a plurality of contacts;
forming a plurality of through silicon vias through the silicon substrate, the embedded interconnect layer being coupled to a first end of the plurality of through silicon vias;
generating one or more conductive paths through the substrate, the generating the one or more conductive paths comprising processing the silicon substrate to expose the through silicon vias on a second, opposite side of the silicon substrate, the one or more conductive paths being connected with the embedded interconnect layer;
forming a redistribution layer (RDL) coupled with a second end of the plurality of through silicon vias at the second side of the silicon substrate; and
applying a conductive adhesive to the second side of the silicon substrate, and coupling the silicon substrate with a wire layer of an organic substrate using the conductive adhesive.

7. The method of claim 6 , wherein the conductive adhesive is an anisotropic conductive adhesive, further comprising applying pressure to the anisotropic conductive adhesive to create an electrical connection by compression of conductive particles.

8. The method of claim 6 , wherein generating the one or more conductive paths includes generating a plurality of conductive paths from the wire layer of the organic substrate to the embedded interconnect layer through the through silicon vias.

9. A method comprising:
providing a substrate;
embedding metal and dielectric layers in a first side of the substrate to form an embedded interconnect layer, the embedded interconnect layer including a plurality of contacts; and
generating one or more conductive paths through the substrate, the one or more conductive paths being connected with the embedded interconnect layers, wherein fabricating the substrate includes:
bonding a conductive bridge substrate to a carrier wafer;
embedding the metal and dielectric layers in a first side of the conductive bridge substrate; and
de-bonding the conductive bridge substrate from the carrier wafer.

10. The method of claim 9 , further comprising applying a conductive adhesive to a second side of the conductive bridge substrate, and coupling the silicon substrate with a wire layer of an organic substrate using the conductive adhesive.

11. The method of claim 10 , wherein generating the one or more conductive paths includes generating a single conductive path from the wire layer of the organic substrate to the embedded interconnect layer through the conductive bridge substrate.

12. A package comprising:
a plurality of chips; an organic substrate; and
an interconnect bridge coupled with the organic substrate to connect one or more of the plurality of chips, the interconnect bridge including:
a substrate, an embedded interconnect layer in a first side of the substrate, the embedded interconnect layer including a plurality of contacts, and one or more conductive paths through the substrate to the organic substrate, the one or more conductive paths being connected with the embedded interconnect layers.

13. The package of claim 12 , wherein the substrate is a silicon substrate including a plurality of through silicon vias, the embedded interconnect layer being coupled to a first end of the plurality of through silicon vias, the bridge interconnect further including:
a redistribution layer coupled with a second end of the plurality of through silicon vias at the second side of the silicon substrate.

14. The package of claim 13 , wherein the interconnect bridge is coupled with a wire layer of the organic substrate using a conductive adhesive applied to the second side of the silicon substrate.

15. The package of claim 14 , wherein the conductive adhesive is an anisotropic conductive adhesive, wherein applying pressure to the anisotropic conductive adhesive creates an electrical connection by compression of conductive particles.

16. The package of claim 12 , wherein the substrate of the interconnect bridge is a conductive substrate, the embedded interconnect layer having an ohmic contact with the conductive substrate.

17. The package of claim 16 , wherein the interconnect bridge is coupled with a wire layer of the organic substrate using a conductive adhesive applied to the second side of the conductive substrate.

Assignees

• Intel Corp

Inventors

• Sankman Robert L
• Elsherbini Adel A

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/698 Primary

  Semiconductor materials that are electrically insulating, e.g. undoped silicon · CPC title