Compression-based scan test system

Patent metadata

Field	Value
Publication number	US-12265121-B2
Application number	US-202318322336-A
Country	US
Kind code	B2
Filing date	May 23, 2023
Priority date	May 23, 2023
Publication date	Apr 1, 2025
Grant date	Apr 1, 2025

Abstract

In accordance with an embodiment, a method for operating a Pseudo-Random Pattern Generator (PRPG) based scan test system includes: generating test patterns using a Pseudo-Random Pattern Generator (PRPG), generating the test patterns including clocking the PRPG using a first clock signal; loading the test patterns into a plurality of scan chains coupled to the PRPG; modifying a bit distribution of the generated test patterns with respect to the plurality of scan chains by freezing at least one clock cycle of the first clock signal while a second clock signal is active or freezing at least one clock cycle of the second clock signal while the first clock signal is active; shifting the loaded test patterns using the second clock signal; applying the test patterns to a circuit under test (CUT) through the plurality of scan chains; and capturing response patterns generated by the CUT in the plurality of scan chains.

First claim

What is claimed is:

1. A method for operating a Pseudo-Random Pattern Generator (PRPG) based scan test system comprising:
generating test patterns using a Pseudo-Random Pattern Generator (PRPG), generating the test patterns comprising clocking the PRPG using a first clock signal;
loading the test patterns into a plurality of scan chains coupled to the PRPG;
shifting the loaded test patterns using a second clock signal;
modifying a bit distribution of the generated test patterns with respect to the plurality of scan chains comprising:
freezing at least one clock cycle of the first clock signal while the second clock signal is active, wherein freezing the at least one clock cycle of the first clock signal causes a same pattern output by the PRPG to be clocked into the plurality of scan chains, or
freezing at least one clock cycle of the second clock signal while the first clock signal is active, wherein freezing the at least one clock cycle of the second clock signal prevents a first pattern output by the PRPG from being clocked into the plurality of scan chains;

applying the test patterns to a circuit under test (CUT) through the plurality of scan chains; and
capturing response patterns generated by the CUT in the plurality of scan chains.

2. The method of claim 1 , further comprising compressing the captured response patterns using a compressor, wherein generating the test patterns comprises decompressing at least one test input pattern using the PRPG.

3. The method of claim 2 , wherein the at least one test input pattern comprises a seed value for the PRPG.

4. The method of claim 2 , wherein generating the test patterns further comprises phase shifting an output of the PRPG.

5. The method of claim 1 , further comprising:
applying the captured response patterns to a compressor; and
clocking the compressor with the first clock signal.

6. The method of claim 5 , wherein the compressor comprises a multiple input signature register (MISR).

7. The method of claim 5 , further comprising determining a presence of faults in the CUT by comparing an output of the compressor to a reference signature.

8. The method of claim 1 , wherein modifying the bit distribution comprises freezing the at least one clock cycle of the second clock signal while the first clock signal is active once every n first clock cycles, wherein n is an integer greater than or equal to zero.

9. The method of claim 8 , further comprising delaying the freezing of at least one clock cycle of the second clock signal by an offset value p, where p is an integer greater than or equal to zero.

10. The method of claim 1 , wherein loading the test patterns into the plurality of scan chains comprises loading the test patterns into a plurality of registers of the plurality of scan chains.

11. The method of claim 1 , further comprising determining a presence of faults in the CUT based on the captured response patterns.

12. The method of claim 1 , wherein modifying the bit distribution of the generated test patterns is configured to increase a temporal proximity of care bits produced by the PRPG.

13. A system comprising:
a test system configured to be coupled to a circuit under test (CUT), the test system comprising:
a pattern generation circuit comprising a Pseudo-Random Pattern Generator (PRPG) coupled to a first clock input;
a plurality of scan chains coupled to an output of the PRPG and configured to be coupled to the CUT, the plurality of scan chains comprising registers having clock inputs coupled to a second clock input;
an evaluation circuit coupled to the plurality of scan chains, the evaluation circuit configured to capture response patterns generated by the CUT in the plurality of scan chains; and
a control circuit configured to modify a bit distribution of test patterns generated by the PRPG with respect to the plurality of scan chains by:
freezing at least one clock cycle of a first clock signal while a second clock signal is active, wherein freezing the at least one clock cycle of the first clock signal is configured to cause a same pattern output by the PRPG to be clocked into the plurality of scan chains, or
freezing at least one clock cycle of the second clock signal while the first clock signal is active, wherein freezing the at least one clock cycle of the second clock signal prevents a first pattern output by the PRPG from being clocked into the plurality of scan chains.

14. The system of claim 13 , wherein:
the pattern generation circuit comprises a decompressor; and
the evaluation circuit comprises a compressor.

15. The system of claim 14 , wherein the compressor comprises a multiple input signature register (MISR).

16. The system of claim 14 , wherein the decompressor comprises:
the PRPG; and
a phase shifter coupled to an output of the PRPG.

17. The system of claim 13 , wherein the control circuit is configured to:
freeze the second clock signal while the first clock signal is active once every n first clock cycles, wherein n is an integer greater than or equal to zero.

18. The system of claim 16 , wherein the control circuit is further configured to delay the frozen at least one clock cycle of the second clock signal by an offset value p, where p is an integer greater than or equal to zero.

19. The system of claim 13 , further comprising the CUT.

20. The system of claim 19 , wherein the test system and the CUT are disposed on a single monolithic integrated circuit.

21. The system of claim 13 , wherein the evaluation circuit is further configured to determine a presence of faults in the CUT based on the captured response patterns.

22. The system of claim 13 , wherein the control circuit is configured to modify the bit distribution of the generated test patterns to increase a temporal proximity of care bits produced by the PRPG.

23. An integrated circuit comprising:
a control circuit configured to produce a modified clock signal based on an input clock signal, and freeze at least one clock cycle of the modified clock signal while the input clock signal is active;
a Pseudo-Random Pattern Generator (PRPG) based decompressor having an input configured to receive at least one seed value, wherein the PRPG-based decompressor comprises a clock input configured to receive the input clock signal;
a plurality of scan chains coupled to the PRPG-based decompressor, the plurality of scan chains having registers with clock inputs configured to receive the modified clock signal, wherein the modified clock signal is configured to prevent a first pattern output by the PRPG from being clocked into the plurality of scan chains when the at least one clock cycle of the modified clock signal is frozen;
a compressor coupled to the plurality of scan chains, the compressor comprising a clock input configured to receive the input clock signal; and
a circuit under test (CUT) coupled to the plurality of scan chains.

24. The integrated circuit of claim 23 , wherein the control circuit is configured to freeze the at least one clock cycle of the modified clock signal while the input clock signal is active once every n first clock cycles, wherein n is an integer greater than or equal to zero.

25. The integrated circuit of claim 23 , wherein the compressor comprises a multiple input signature register (MISR).

26. The integrated circuit of claim 23 , wherein the control circuit is configured freeze the at least one clock cyc

Assignees

• St Microelectronics Int Nv

Inventors

• Jain Sandeep
• Pathak Shalini
• Singh Prateek

Classifications

• G01R31/318552

  Clock circuits details · CPC title

• G01R31/318536

  Scan chain arrangements, e.g. connections, test bus, analog signals · CPC title

• G01R31/31813 Primary

  Test pattern generators · CPC title

• G01R31/31727

  Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title

• G01R31/318385

  Random or pseudo-random test pattern · CPC title