Semiconductor device

Patent metadata

Field	Value
Publication number	US-11262403-B2
Application number	US-202016797454-A
Country	US
Kind code	B2
Filing date	Feb 21, 2020
Priority date	Sep 2, 2019
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

According to one embodiment, a semiconductor device includes: a first scan chain and a second scan chain each including a plurality of cascaded flip-flops; a plurality of power supply lines that supply a power supply voltage to the first and second scan chains, extend in a first direction, and are arranged in a second direction intersecting with the first direction; and a clock control circuit that supplies a first clock to the first scan chain and a second clock to the second scan chain, the second clock having timing different to that of the first clock. The plurality of flip-flops are arranged along the second direction.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first scan chain and a second scan chain each including a plurality of cascaded flip-flops;
a plurality of power supply lines that supply a power supply voltage to the first and second scan chains, extend in a first direction, and are arranged in a second direction intersecting with the first direction;
a first signal line coupled to a clock terminal of the first scan chain;
a second signal line coupled to a clock terminal of the second scan chain; and
a clock control circuit that supplies a first clock to the first signal line and a second clock to the second signal line, the second clock having timing different to that of the first clock, wherein
each of the power supply lines is connected to a group of flip-flops arranged in the first direction, and
the plurality of cascaded flip-flops are arranged along the second direction.

2. The semiconductor device according to claim 1 , wherein
the plurality of cascaded flip-flops are arranged in such a manner that a maximum of two flip-flops are coupled to one power supply line.

3. The semiconductor device according to claim 1 , further comprising:
a first interconnect coupled to the plurality of power supply lines in common and extending in the second direction.

4. The semiconductor device according to claim 1 , further comprising:
a plurality of ground lines that supply a ground voltage to the first and second scan chains, extend in the first direction, and are arranged in the second direction.

5. The semiconductor device according to claim 4 , further comprising:
a second interconnect coupled to the plurality of ground lines in common and extending in the second direction.

6. The semiconductor device according to claim 1 , further comprising:
a generator that supplies a test pattern to the first and second scan chains; and
a compressor that compresses a pattern output from the first and second scan chains.

7. A semiconductor device comprising:
a first scan chain and a second scan chain that each includes a plurality of cascaded flip-flops;
a plurality of power supply lines that supply a power supply voltage to the first and second scan chains, extend in a first direction, and are arranged in a second direction intersecting with the first direction;
a first signal line coupled to a clock terminal of the first scan chain;
a second signal line coupled to a clock terminal of the second scan chain;
a first delay element coupled between the first scan chain and the second scan chain;
a second delay element coupled between the first signal line and the second signal line; and
a clock control circuit that supplies a clock to the first signal line, wherein
each of the power supply lines is connected to a group of flip-flops arranged in the first direction, and
the plurality of cascaded flip-flops are arranged along the second direction.

8. The semiconductor device according to claim 7 , wherein
the first delay element is arranged at an edge of the first scan chain.

9. The semiconductor device according to claim 7 , wherein
the first delay element is arranged at a location other than an edge of the first scan chain.

10. The semiconductor device according to claim 7 , wherein
the plurality of cascaded flip-flops are arranged in such a manner that a maximum of two flip-flops are coupled to one power supply line.

11. The semiconductor device according to claim 7 , further comprising:
a first interconnect coupled to the plurality of power supply lines in common and extending in the second direction.

12. The semiconductor device according to claim 7 , further comprising:
a plurality of ground lines that supply a ground voltage to the first and second scan chains, extend in the first direction, and are arranged in the second direction.

13. The semiconductor device according to claim 12 , further comprising:
a second interconnect coupled to the plurality of ground lines in common and extending in the second direction.

14. The semiconductor device according to claim 7 , further comprising:
a generator that generates a test pattern for the first scan chain; and
a compressor that compresses a pattern output from the second scan chain.

15. A semiconductor device comprising:
a first scan chain and a second scan chain that each includes a plurality of cascaded flip-flops;
a plurality of power supply lines that supply a power supply voltage to the first and second scan chains, extend in a first direction, and are arranged in a second direction intersecting with the first direction;
a latch circuit coupled between the first scan chain and the second scan chain;
a first signal line coupled to a clock terminal of the first scan chain;
a second signal line coupled to a clock terminal of the second scan chain and a clock terminal of the latch circuit;
a delay element coupled between the first signal line and the second signal line; and
a clock control circuit that supplies a clock to the first signal line, wherein
each of the power supply lines is connected to a group of flip-flops arranged in the first direction, and
the plurality of cascaded flip-flops are arranged along the second direction.

16. The semiconductor device according to claim 15 , wherein
the plurality of cascaded flip-flops are arranged in such a manner that maximum two of the flip-flops are coupled to one power supply line.

17. The semiconductor device according to claim 15 , further comprising:
a first interconnect coupled to the plurality of power supply lines in common and extending in the second direction.

18. The semiconductor device according to claim 15 , further comprising:
a plurality of ground lines that supply a ground voltage to the first and second scan chains, extend in the first direction, and are arranged in the second direction.

19. The semiconductor device according to claim 18 , further comprising:
a second interconnect coupled to the plurality of ground lines in common and extending in the second direction.

20. The semiconductor device according to claim 15 , further comprising:
a generator that generates a test pattern for the first scan chain; and
a compressor that compresses a pattern output from the second scan chain.

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Watanabe Yuki
• Dozaka Toshiaki

Classifications

• G01R31/318552 Primary

  Clock circuits details · CPC title

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/318555

  Control logic · CPC title

• G01R31/318536 Primary

  Scan chain arrangements, e.g. connections, test bus, analog signals · CPC title

• G01R31/318541

  Scan latches or cell details · CPC title