Complementary storage unit and method of preparing the same, and complementary memory

Patent metadata

Field	Value
Publication number	US-12260902-B2
Application number	US-202018042574-A
Country	US
Kind code	B2
Filing date	Aug 24, 2020
Priority date	Aug 24, 2020
Publication date	Mar 25, 2025
Grant date	Mar 25, 2025

Abstract

A complementary storage unit and a method of preparing the same, and a complementary memory. The complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode. The control transistor is configured to control reading and writing of the storage unit. One end of the pull-up diode is connected to a positive selection line, and the other end thereof is connected to a source end of the control transistor, so as to control a high-level input. One end of the pull-down diode is connected to a negative selection line, and the other end thereof is connected to the source end of the control transistor, so as to control a low-level input. The pull-up diode and the pull-down diode are symmetrically arranged in a first direction.

First claim

What is claimed is:

1. A complementary storage unit, comprising:
a control transistor configured to control reading and writing of the storage unit;
a pull-up diode, wherein one end of the pull-up diode is connected to a positive selection line, and the other end of the pull-up diode is connected to a source end of the control transistor, so as to control a high-level input; and
a pull-down diode, wherein one end of the pull-down diode is connected to a negative selection line, and the other end of the pull-down diode is connected to the source end of the control transistor, so as to control a low-level input;
wherein the pull-up diode and the pull-down diode are symmetrically arranged in a first direction.

2. The complementary storage unit according to claim 1 , wherein a drain end of the control transistor is connected to a bit line, and a gate electrode of the control transistor is connected to a word line.

3. The complementary storage unit according to claim 2 ,
wherein when a storage state of the complementary storage unit is 1, turning-on directions of the pull-up diode and the pull-down diode point toward the source end of the control transistor; and
wherein when the storage state of the complementary storage unit is 0, the turning-on direction of the pull-up diode points toward the positive selection line, and the turning-on direction of the pull-down diode points toward the negative selection line.

4. The complementary storage unit according to claim 2 ,
wherein when a writing state of the complementary storage unit is 1, the word line is applied with a turning-on voltage VDD, the bit line is applied with a writing voltage V write , and the positive selection line and the negative selection line are grounded; and
wherein when the writing state of the complementary storage unit is 0, the word line is applied with the turning-on voltage V DD , the bit line is grounded, and the positive selection line and the negative selection line are applied with the writing voltage V write .

5. The complementary storage unit according to claim 2 ,
wherein when the complementary storage unit is in a reading state, the word line is applied with a turning-on voltage V DD , the positive selection line is applied with an input voltage Vin, and the negative selection line is grounded,
wherein when a storage state of the complementary storage unit is 1, an output voltage output by the bit line is high level; and
wherein when the storage state of the complementary storage unit is 0, the output voltage output by the bit line is low level.

6. The complementary storage unit according to claim 2 , wherein when the complementary storage unit is not selected,
the word line is grounded; or
the bit line is applied with a protection voltage V B , wherein V B =(½) V write .

7. The complementary storage unit according to claim 1 ,
wherein the control transistor is a MOS transistor; and
wherein the pull-up diode and the pull-down diode are the same programmable diode.

8. The complementary storage unit according to claim 7 , wherein the programmable diode comprises:
a lower electrode layer configured to support the programmable diode and provide a lower electrode of the programmable diode;
a dielectric layer formed on the lower electrode layer and configured as a functional layer of the programmable diode to maintain a stable state after canceling an electrical signal; and
an upper electrode layer formed on the dielectric layer and configured to provide an upper electrode of the programmable diode.

9. The complementary storage unit according to claim 8 ,
wherein the lower electrode layer is made of at least one of W, Al, Ti, Ta, Ni, Hf, TiN, and TaN;
wherein the dielectric layer is made of a dielectric material with charged defects, or at least one material having ferroelectric characteristics which is selected from a perovskite type ferroelectric material, a ferroelectric polymer PVDF material and a HfO 2 based ferroelectric material; and
wherein the upper electrode layer is made of at least one of W, Al, Cu, Ru, Ti, Ta, TiN, TaN, IrO 2 , ITO, and IZO.

10. The complementary storage unit according to claim 9 , wherein the HfO 2 based ferroelectric material is a HfO 2 based material doped with at least one element of Zr, Al, Si, and La.

11. A complementary memory, having an array structure formed of a plurality of complementary storage units according to claim 1 .

12. A method of preparing the complementary storage unit according to claim 1 , comprising:
forming a control transistor, wherein the control transistor is configured to control reading and writing of the storage unit; and
symmetrically forming a pull-up diode and a pull-down diode on the control transistor in a first direction.

Assignees

• Inst Of Microelectronics Cas

Inventors

• Luo Qing
• Chen Bing
• Lv Hangbing
• Liu Ming
• Lu Cheng

Classifications

• H03K19/01742 Primary

  by means of a pull-up or down element · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• H10D1/682

  having dielectrics comprising perovskite structures · CPC title

• H10B53/30

  characterised by the memory core region · CPC title