3D stackable memory and methods of manufacture

Patent metadata

Field	Value
Publication number	US-11729997-B2
Application number	US-202117229395-A
Country	US
Kind code	B2
Filing date	Apr 13, 2021
Priority date	Jun 29, 2020
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

Memory devices and methods of forming the memory devices are disclosed herein. The memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. The memory devices further include a first diode and a second diode over the inter-metal dielectric layer. The memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.

First claim

What is claimed is:

1. A memory device comprising:
a resistive memory array comprising a first resistive memory cell;
a staircase contact structure adjacent the resistive memory array;
an inter-metal dielectric layer over the staircase contact structure;
a first diode and a second diode over the inter-metal dielectric layer;
a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell; and
a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.

2. The memory device of claim 1 , wherein the first conductive via is connected to a first top electrode of the first resistor and wherein the second conductive via is connected to a second top electrode of the second resistor.

3. The memory device of claim 2 , wherein a first bit line is electrically coupled to the first resistor and a second bit line is electrically coupled to the second resistor, wherein the first bit line and the second bit line are at least partially disposed in the first resistive memory cell.

4. The memory device of claim 3 , wherein the first bit line is connected to a first resistive memory film of the first resistor and wherein the second bit line is connected to a second resistive memory film of the second resistor.

5. The memory device of claim 4 , wherein the first resistive memory cell comprises a first transistor, the memory device further comprising:
a third conductive via connected to a first source line that is electrically coupled to the first transistor; and
a fourth conductive via connected to a second source line that is electrically coupled to the first transistor.

6. The memory device of claim 5 , wherein the first transistor comprises a gate dielectric surrounding a channel region of the first transistor and a wrap-around gate, wherein the channel region of the first transistor separates the first source line from the second source line and separates the first bit line from the second bit line.

7. The memory device of claim 6 further comprises:
a second resistive memory cell over the first resistive memory cell;
a third diode and a fourth diode over the inter-metal dielectric layer;
a fifth conductive via electrically coupling the third diode to a third resistor of the second resistive memory cell; and
a sixth conductive via electrically coupling the fourth diode to a fourth resistor of the second resistive memory cell.

8. A memory device comprising:
a first memory cell comprising a first transistor, a first resistor, and a second resistor, wherein the first resistor is coupled to a first bit line and the second resistor is coupled to a second bit line;
a first diode connected to a first electrode of the first resistor;
a second diode connected to a second electrode of the second resistor, the first electrode of the first resistor being over the second electrode of the second resistor;
a first conductive via connected to the first diode;
a second conductive via connected to the second diode; and
an inter-metal dielectric layer, wherein the first diode, the second diode, the first conductive via, and the second conductive via are embedded in the inter-metal dielectric layer.

9. The memory device of claim 8 , wherein the first diode comprises a first conductive type semiconductor oxide layer adjacent the first electrode of the first resistor.

10. The memory device of claim 9 , wherein the first diode comprises a second conductive type semiconductor oxide layer adjacent the first conductive type semiconductor oxide layer.

11. The memory device of claim 10 , wherein the first conductive type semiconductor oxide layer is a p-type and the second conductive type semiconductor oxide layer is an n-type.

12. The memory device of claim 11 , further comprising:
a third conductive via connected to a first source line; and
a fourth conductive via connected to a second source line, the third conductive via and the fourth conductive via being embedded in the inter-metal dielectric layer.

13. The memory device of claim 12 , wherein the first transistor comprises a wrap-around gate surrounding a first channel region of the first transistor.

14. The memory device of claim 13 , further comprising:
a second memory cell over the first memory cell, the second memory cell comprising a second transistor, a third resistor, and a fourth resistor, wherein the third resistor is coupled to a third bit line and the fourth resistor is coupled to a fourth bit line;
a third diode connected to a third electrode of the third resistor;
a fourth diode connected to a fourth electrode of the fourth resistor, the third electrode of the third resistor being over the fourth electrode of the fourth resistor;
a fifth conductive via connected to the third diode; and
a sixth conductive via connected to the fourth diode, wherein the third diode, the fourth diode, the fifth conductive via, and the sixth conductive via are embedded in the inter-metal dielectric layer.

15. The memory device of claim 14 , wherein the wrap-around gate surrounds a second channel region of the second transistor.

16. A method comprising:
forming a resistive memory array in a first region of a multilayer stack of materials, the resistive memory array comprising a first memory cell;
exposing a first resistor and a second resistor of the first memory cell by forming a staircase contact structure adjacent the resistive memory array;
forming a first diode over the staircase contact structure, the first diode being electrically coupled to the first resistor; and
forming a second diode over the staircase contact structure, the second diode being electrically coupled to the second resistor.

17. The method of claim 16 , further comprising:
forming an inter-metal dielectric layer over the staircase contact structure;
forming a first contact via through the inter-metal dielectric layer to the first resistor; and
forming a second contact via through the inter-metal dielectric layer to the second resistor, wherein forming the first diode and the second diode comprises:
depositing a first conductive type semiconductor oxide layer over the inter-metal dielectric layer;
depositing a second conductive type semiconductor oxide layer over the first conductive type semiconductor oxide layer; and
forming the first diode connected to the first contact via and forming the second diode connected to the second contact via by patterning the first and second conductive type semiconductor oxide layers.

18. The method of claim 16 , wherein forming the first diode comprises forming the first diode in direct contact with the first resistor, wherein forming the second diode comprises forming the second diode in direct contact with the second resistor, and wherein the method further comprises:
forming an inter-metal dielectric layer over the first diode, the second diode, and the staircase contact structure;
forming a first contact via through the inter-metal dielectric layer to the first diode; and
forming a second contact via through the inter-metal dielectric layer to the second diode.

19. The method of claim 16 , further comprising:
forming an inter-metal dielectric layer over the staircase contact structure;
exposing the first resistor and the second resistor by forming openings in the inter-metal dielectric layer;
forming diodes by depositing a first conductive type semiconductor oxide material over the first resistor and the second resistor at bottoms of the openings and dep

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Meng-Han
• Chang Chih-Yu
• Chia Han-Jong
• Yeong Sai-Hooi
• Lin Yu-Ming

Classifications

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D88/01

  Manufacture or treatment · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title