Nonvolatile memory device and storage device having the same

Patent metadata

Field	Value
Publication number	US-9431083-B2
Application number	US-201514593171-A
Country	US
Kind code	B2
Filing date	Jan 9, 2015
Priority date	Mar 25, 2014
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

A nonvolatile memory device according to the inventive concepts performs a read operation from a true cell storing data and complementary cell storing complementary data, thereby increasing or maximizing sensing margin. Also, the nonvolatile memory device connects a plurality of true cell/complementary cells to a word line, thereby markedly reducing the size of a memory cell array.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
first and second true cells storing data;
first and second complementary cells storing complementary data of the data;
bit lines respectively connected to first ends of the first and second true cells;
complementary bit lines respectively connected to first ends of the first and second complementary cells;
a first sub word line connected to second ends of the first true cells;
a second sub word line connected to second ends of the second true cells;
a first complementary sub word line connected to second ends of the first complementary cells;
a second complementary sub word line connected to second ends of the second complementary cells; and
a first transistor configured to connect the first sub word line to a first source line in response to a first on voltage applied to a first word line;
a first complementary transistor configured to connect the first complementary sub word line to a first complementary source line in response to the first on voltage;
a second transistor configured to connect the second sub word line to the first source line in response to a second on voltage applied to a second word line; and
a second complementary transistor configured to connect the second complementary sub word line to the first complementary source line in response to the second on voltage.

2. The nonvolatile memory device of claim 1 , wherein each of the first and second true cells and the first and second complementary cells is a magnetic tunnel junction (MTJ) cell.

3. The nonvolatile memory device of claim 2 , wherein the first and second word lines extend in a same direction as that of the first source line and the second complementary source line.

4. The nonvolatile memory device of claim 1 , further comprising:
bit line selection transistors configured to selectively connect one of the bit lines to a first data line in response to column selection signals; and
complementary bit line selection transistors configured to selectively connect one of the complementary bit lines to a second data line in response to the column selection signals.

5. The nonvolatile memory device of claim 4 , further comprising:
an input buffer providing the first data line with a voltage corresponding to the data; and
a complementary input buffer providing the second data line with a voltage corresponding to the complementary data.

6. The nonvolatile memory device of claim 5 , wherein after a pre-charge voltage is applied to the bit lines in a writing operation about one of the first and second true cells, a ground voltage is applied to a selected bit line, an on voltage is applied to a selected word line, and a write voltage is applied to the first source line.

7. The nonvolatile memory device of claim 5 , wherein after a ground voltage is applied to the complementary bit lines in a writing operation about one of the first and second complementary cells, the pre-charge voltage is applied to a selected complementary bit line, an on voltage is applied to a selected word line, and a ground voltage is applied to the first complementary source line.

8. The nonvolatile memory device of claim 4 , further comprising:
a sense amplifier configured to sense voltage or current at the first data line and the second data line.

9. The nonvolatile memory device of claim 8 , wherein after a ground voltage is applied to the bit lines at a reading operation about one of the first and second true cells, an on voltage is applied to a selected word line, and a ground voltage is applied to the first source line.

10. The nonvolatile memory device of claim 8 , wherein after a ground voltage is applied to the complementary bit lines at a reading operation about one of the first and second complementary cells, an on voltage is applied to a selected word line, and a ground voltage is applied to the first complementary source line.

11. The nonvolatile memory device of claim 1 , further comprising:
a source line control circuit configured to control a voltage applied to the first source line and the first complementary source line independently in response to source line control signals.

12. The nonvolatile memory device of claim 11 , further comprising:
a source line control signal generator configured to generate the source line control signals in response to data, a read enable signal, and a write enable signal.

13. The nonvolatile memory device of claim 1 , wherein the on voltage is a power supply voltage.

14. A non-volatile memory device, comprising:
a source line structure;
a plurality of true memory cells connected between first respective bit lines and a sub word line structure;
a plurality of complementary memory cells connected between respective complementary bit lines and the sub word line structure;
a selection structure configured to selectively electrically connect the source line structure to the sub word line structure;
a control circuit configured to control the selection structure during at least one of a read operation and a write operation such that a first sub word line in the sub word line structure is connected to a first source line in the source line structure and a second sub word line in the sub word line structure is connected to a second source line in the source line structure based on application of an on voltage to a single word line, the first sub word line connected to the plurality of true memory cells, and the second sub word line connected to the plurality of complementary memory cells.

15. The non-volatile memory device of claim 14 , wherein the first sub word line and the second sub word line are one of a same sub word line and different sub word lines, and the first source line and the second source line are one of a same source line and different source lines.

Assignees

• Pyo Suk-Soo
• Jung Hyuntaek
• Samsung Electronics Co Ltd

Inventors

• Pyo Suk-Soo
• Jung Hyuntaek

Classifications

• G11C11/1659

  Cell access · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G11C11/1673 Primary

  Reading or sensing circuits or methods · CPC title

• G11C7/062

  Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs · CPC title