Semiconductor package and package-on-package including the same

Patent metadata

Field	Value
Publication number	US-12255160-B2
Application number	US-202217742862-A
Country	US
Kind code	B2
Filing date	May 12, 2022
Priority date	Aug 9, 2021
Publication date	Mar 18, 2025
Grant date	Mar 18, 2025

Abstract

Provided is a semiconductor package including a pair of differential signal wiring lines including a first differential signal wiring line and a second differential signal wiring line, extending parallel to and spaced apart from each other, a lower equal potential plate in a lower wiring layer under the signal wiring layer, an upper equal potential plate in an upper wiring layer above the signal wiring layer, and a wiring insulating layer adjacent to the pair of differential signal wiring lines, the lower equal potential plate, and the upper equal potential plate, the wiring insulating layer filling spaces between the signal wiring layer, the lower wiring layer, and the upper wiring layer, at least one of the lower equal potential plate and the upper equal potential plate including an impedance opening overlapping the pair of differential signal wiring lines in a vertical direction and is filled by the wiring insulating layer.

First claim

What is claimed is:

1. A semiconductor package comprising:
a pair of differential signal wiring lines in a signal wiring layer, the pair of differential signal wiring lines comprising a first differential signal wiring line and a second differential signal wiring line which extend parallel to and spaced apart from each other;
a lower equal potential plate in a lower wiring layer that is under the signal wiring layer;
an upper equal potential plate in an upper wiring layer that is above the signal wiring layer opposite to the lower equal potential plate; and
a wiring insulating layer adjacent to the pair of differential signal wiring lines, the lower equal potential plate, and the upper equal potential plate,
wherein the wiring insulating layer fills spaces between the signal wiring layer, the lower wiring layer, and the upper wiring layer, and
wherein at least one of the lower equal potential plate and the upper equal potential plate comprises an impedance opening which overlaps the pair of differential signal wiring lines in a vertical direction and is filled by the wiring insulating layer.

2. The semiconductor package of claim 1 , wherein the impedance opening comprises a lower impedance opening in the lower equal potential plate and an upper impedance opening in the upper equal potential plate, and
wherein the pair of differential signal wiring lines do not overlap the lower equal potential plate and the upper equal potential plate in the vertical direction.

3. The semiconductor package of claim 2 , further comprising:
a lower redistribution layer comprising the signal wiring layer, the lower wiring layer, a lower redistribution insulating layer, and a lower redistribution conductive structure that comprises the pair of differential signal wiring lines;
an expanded layer comprising the upper wiring layer, a substrate base, a wiring structure, and the upper equal potential plate; and
a semiconductor chip on the lower redistribution layer,
wherein a lower portion of the wiring insulating layer is a portion of the lower redistribution insulating layer, and an upper portion of the wiring insulating layer is a portion of the substrate base.

4. The semiconductor package of claim 3 , wherein the lower impedance opening overlaps the pair of differential signal wiring lines in the vertical direction and extends from a lower side of the semiconductor chip to a lower side of the expanded layer, and
wherein the upper impedance opening in the expanded layer overlaps portions of the pair of differential signal wiring lines in the vertical direction.

5. The semiconductor package of claim 3 , wherein a material of the lower portion of the wiring insulating layer is different from a material of the upper portion of the wiring insulating layer.

6. The semiconductor package of claim 1 , wherein a thickness of the upper equal potential plate is greater than a thickness of the lower equal potential plate.

7. The semiconductor package of claim 1 , wherein the impedance opening comprises a lower impedance opening in the lower equal potential plate, and
wherein the pair of differential signal wiring lines overlap the upper equal potential plate in the vertical direction and do not overlap the lower equal potential plate in the vertical direction.

8. The semiconductor package of claim 1 , wherein the impedance opening comprises an upper impedance opening in the upper equal potential plate, and
wherein the pair of differential signal wiring lines overlap the lower equal potential plate in the vertical direction and do not overlap the upper equal potential plate in the vertical direction.

9. The semiconductor package of claim 1 , further comprising an equal potential bridge extending to bisect the impedance opening, the equal potential bridge being integrally formed with at least one of the lower equal potential plate and the upper equal potential plate.

10. The semiconductor package of claim 9 , wherein the equal potential bridge overlaps a space between the first differential signal wiring line and the second differential signal wiring line in the vertical direction.

11. A semiconductor package comprising:
a lower redistribution layer comprising:
a plurality of lower redistribution line patterns;
a plurality of lower redistribution via patterns;
a lower equal potential plate;
a lower redistribution insulating layer adjacent to the plurality of lower redistribution line patterns, the plurality of lower redistribution via patterns, and the lower equal potential plate;
a signal wiring layer; and
a lower wiring layer under the signal wiring layer,
wherein a pair of differential signal wiring lines are portions of the plurality of lower redistribution line patterns in the signal wiring layer, and the lower equal potential plate is in the lower wiring layer, and
wherein the pair of differential signal wiring lines comprise a first differential signal wiring line and a second differential signal wiring line, which extend spaced apart from each other;

an expanded layer overlapping portions of the pair of differential signal wiring lines in a vertical direction, the expanded layer comprising:
a substrate base having a mounting space;
a plurality of wiring patterns and an upper equal potential plate on at least one of a top surface and a bottom surface of the substrate base;
a plurality of conductive vias passing through at least a portion of the substrate base; and
an upper wiring layer in which the upper equal potential plate is provided, the upper wiring layer being above the signal wiring layer; and

a semiconductor chip in the mounting space on the lower redistribution layer,
wherein the lower equal potential plate and the upper equal potential plate respectively have a lower impedance opening and an upper impedance opening, and
wherein the lower impedance opening and the upper impedance opening overlap at least portions of the pair of differential signal wiring lines in the vertical direction.

12. The semiconductor package of claim 11 , wherein the lower redistribution layer further comprises a single signal wiring line in the signal wiring layer, the single signal wiring line being spaced apart from the pair of differential signal wiring lines, and
wherein the single signal wiring line overlaps the lower equal potential plate and the upper equal potential plate in the vertical direction.

13. The semiconductor package of claim 11 , wherein the lower impedance opening overlaps the pair of differential signal wiring lines in the vertical direction and extends from a lower side of the semiconductor chip to a lower side of the expanded layer, and
wherein the upper impedance opening in the expanded layer overlaps portions of the pair of differential signal wiring lines and a portion of the lower impedance opening in the vertical direction.

14. The semiconductor package of claim 11 , wherein the lower redistribution layer further comprises a lower equal potential bridge extending to bisect the lower impedance opening, the lower equal potential bridge being integrally formed with the lower equal potential plate,
wherein the expanded layer further comprises an upper equal potential bridge extending to bisect the upper impedance opening, the upper equal potential bridge being integrally formed with the upper equal potential plate, and
wherein the lower equal potential bridge and the upper equal potential bridge overlap a space between the first differential signal wiring line and the second differential signal wiring line in the vertical direction.

15. The semiconductor package of claim 14 , wherein a

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Juyoun
• Lee Eunjung
• Lee Junho
• Ha Seungsoo

Classifications

• H10W44/223

  Differential pair signal lines · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/30

  Die-attach connectors · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title