Dummy features in redistribution layers (RDLS) and methods of forming same

Patent metadata

Field	Value
Publication number	US-9997464-B2
Application number	US-201615225024-A
Country	US
Kind code	B2
Filing date	Aug 1, 2016
Priority date	Apr 29, 2016
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.

First claim

What is claimed is:

1. A device comprising:
an integrated circuit die;
a first insulating layer over the integrated circuit die;
a first metallization pattern in the first insulating layer over the integrated circuit die, wherein the first metallization pattern comprises:
a first dummy pattern defining a first hole extending through a first conductive region; and
a first signal line electrically connected to the integrated circuit die;

a second insulating layer over the first insulating layer and the first metallization pattern; and
a second metallization pattern in the second insulating layer over the first metallization pattern, wherein the second metallization pattern comprises a second dummy pattern defining a second hole extending through a second conductive region, and wherein the second hole projectively overlaps a portion of the first hole and a portion of the first conductive region.

2. The device of claim 1 , wherein the first conductive region comprises a dummy line bounding a side of the first hole, and wherein a line extending through a center of the dummy line also extends through a center of the second hole in a cross-sectional view of the device.

3. The device of claim 1 , wherein the first conductive region comprises a dummy line bounding a side of the first hole, and wherein a line extending through a center of the dummy line does not extend through a center of the second hole in a cross-sectional view of the device.

4. The device of claim 1 , further comprising a via extending through the second metallization pattern, wherein the via electrically connects the first signal line to a second signal line disposed over the second metallization pattern.

5. The device of claim 1 , wherein the second conductive region completely covers the first signal line.

6. The device of claim 1 , wherein the first dummy pattern, the second dummy pattern, or a combination thereof are electrically insulated from any active devices in the integrated circuit die.

7. A package comprising:
an integrated circuit die;
an encapsulant extending along sidewalls of the integrated circuit die;
a through via extending through the encapsulant and electrically connected to the integrated circuit die;
a first dielectric layer over the integrated circuit die and the encapsulant;
a first dummy pattern in the first dielectric layer, wherein the first dummy pattern comprises:
a first conductive material; and
a plurality of first holes extending through the first conductive material and disposed in a first grid of first rows and columns;

a second dielectric layer over the first dielectric layer; and
a second dummy pattern in the second dielectric layer, wherein the second dummy pattern comprises:
a second conductive material; and
a plurality of second holes extending through the second conductive material and disposed in a second grid of second rows and columns, wherein the second grid is offset from the first grid.

8. The package of claim 7 further comprising:
a third dielectric layer over the second dielectric layer; and
a third dummy pattern in the third dielectric layer, wherein the third dummy pattern comprises:
a third conductive material; and

a plurality of third holes extending through the third conductive material and disposed in a third grid of third rows and columns, wherein the second grid is offset from the third grid.

9. The package of claim 8 , wherein the third grid is substantially aligned with the first grid.

10. The package of claim 7 , wherein the second conductive material comprises a region free of any holes, and wherein a surface area of the region is at least as large as a surface area of one of the second holes.

11. The package of claim 10 , wherein the region is disposed directly over a first signal line in the first dielectric layer, and wherein the first signal line is electrically connected to an active device in the integrated circuit die.

12. The package of claim 11 further comprising a via extending through the region, wherein the via electrically connects the first signal line to a second signal line in a third dielectric layer over the second dielectric layer.

13. The package of claim 7 , wherein the first dummy pattern does not provide electrical routing between features within the first dielectric layer, and wherein the second dummy pattern does not provide electrical routing between features within the second dielectric layer.

14. The package of claim 7 , wherein a first line disposed halfway between adjacent ones of the first plurality of holes is spaced apart from a second line disposed halfway between adjacent ones of the second plurality of holes by a first dimension in a first direction, wherein a side of one of the second plurality of holes has a second dimension measured in the first direction, and wherein the first dimension is at least half of the second dimension.

15. A method for forming a package, the method comprising:
encapsulating an integrated circuit die in an encapsulant;
depositing a first dielectric layer over the integrated circuit die and the encapsulant;
forming a first metallization pattern over the first dielectric layer, wherein the first metallization pattern comprises:
a first dummy pattern comprising first holes extending through a first conductive material, wherein the first conductive material comprises a first dummy line disposed between adjacent ones of the first holes; and
a first signal line electrically connected to the integrated circuit die;

depositing a second dielectric layer over the first dielectric layer and the first metallization pattern; and
forming a second metallization pattern over the second dielectric layer, wherein the second metallization pattern comprises a second dummy pattern comprising second holes extending through a second conductive material, wherein a line perpendicular to a major surface of the second dielectric layer extends through a first one of the second holes and the first dummy line.

16. The method of claim 15 , wherein the first dummy pattern and the first signal line are formed simultaneously.

17. The method of claim 15 , wherein the line extends through a center of the first dummy line and a center of the first one of the second holes in a cross-sectional view of the package.

18. The method of claim 15 further comprising:
depositing a third dielectric layer over the second metallization pattern;
forming a third metallization pattern over the second metallization pattern, wherein the third metallization pattern comprises:
a third dummy pattern comprising third holes extending through a third conductive material, wherein the third conductive material comprises a second dummy line disposed between adjacent ones of the third holes, and wherein the line extends through the second dummy line; and
a second signal line electrically connected to the first signal line.

19. A method of claim 18 , wherein forming the third metallization pattern comprises:
patterning an opening in the third dielectric layer to expose a portion of the second dummy pattern electrically connected to the first signal line; and
filling the opening with a conductive material.

20. The method of claim 15 , wherein a portion of the second conductive material covers an entirety of the first signal line.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsieh Cheng-Hsien
• Hsu Li-Han
• Wu Wei-Cheng
• Chen Hsien-Wei
• Yeh Der-Chyang
• Wu Chi-Hsi
• Yu Chen-Hua

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title