Semiconductor package

Patent metadata

Field	Value
Publication number	US-10985091-B2
Application number	US-201916691910-A
Country	US
Kind code	B2
Filing date	Nov 22, 2019
Priority date	Dec 18, 2018
Publication date	Apr 20, 2021
Grant date	Apr 20, 2021

Abstract

This invention provides a semiconductor package, the semiconductor package includes: a semiconductor chip having a connection pad; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the semiconductor chip and the encapsulant. The connection structure comprises a first insulation layer, a first redistribution layer disposed on the first insulation layer, and a second insulation layer disposed on the first insulation layer and covering the first redistribution layer. The first redistribution layer has one or more openings. The openings have a shape having a plurality of protrusions, respectively, and B/A is 1.5 or less, where A refers to a thickness of the first redistribution layer, and B refers to a thickness of a region of the second insulation layer covering the first redistribution layer.

First claim

What is claimed is:

1. A semiconductor package comprising:
a semiconductor chip having a connection pad;
an encapsulant covering at least a portion of the semiconductor chip; and
a connection structure disposed on the semiconductor chip and the encapsulant,
wherein the connection structure comprises a first insulation layer, a first redistribution layer disposed on the first insulation layer, and a second insulation layer disposed on the first insulation layer and covering the first redistribution layer,
the first redistribution layer has one or more openings,
the openings have a shape having a plurality of protrusions, respectively, and
B/A is 1.5 or less, where A refers to a thickness of the first redistribution layer, and B refers to a thickness of a region of the second insulation layer covering the first redistribution layer.

2. The semiconductor package according to claim 1 , wherein the B/A is 0.5 or more.

3. The semiconductor package according to claim 1 , wherein the thickness of the first redistribution layer is 10 μm or less.

4. The semiconductor package according to claim 3 , wherein the thickness of the first redistribution layer is 1 μm or more.

5. The semiconductor package according to claim 1 , wherein the openings have a cross shape.

6. The semiconductor package according to claim 1 , wherein the second insulation layer fills at least a portion of each of the openings.

7. The semiconductor package according to claim 1 , wherein the first and second insulation layers are photosensitive insulation layers.

8. The semiconductor package according to claim 1 ,
wherein the connection structure further comprises a second redistribution layer disposed on the second insulation layer, and
wherein the second redistribution layer comprises one or more wiring patterns, wherein at least a portion thereof respectively overlap the openings, in a plan view.

9. The semiconductor package according to claim 8 , wherein widths of the wiring patterns are 10 μm or less, respectively.

10. The semiconductor package according to claim 9 , wherein widths of the wiring patterns are 1 μm or more, respectively.

11. The semiconductor package according to claim 8 ,
wherein the second redistribution layer, in the plan view, comprises:
a first wiring pattern having at least portions respectively overlapping a center of the opening and end portions of at least two protrusions among the plurality of protrusions;
a second wiring pattern disposed on one side of the first wiring pattern and having least a portion overlapping an end portion of one protrusion among the plurality of protrusions; and
a third wiring pattern disposed on the other side of the first wiring pattern and having at least a portion overlapping an end portion of the other protrusion among the plurality of protrusions.

12. The semiconductor package according to claim 8 ,
wherein the second redistribution layer, in the plan view, comprises:
a first wiring pattern overlapping a center of the opening and spaced apart from end portions of the plurality of protrusions;
a second wiring pattern disposed on one side of the first wiring pattern and having at least portions respectively overlapping end portions of two protrusions among the plurality of protrusions; and
a third wiring pattern disposed on the other side of the first wiring pattern and having at least portions respectively overlapping end portions of the other two protrusions among the plurality of protrusions.

13. The semiconductor package according to claim 1 , further comprising a frame having a through-hole,
wherein the semiconductor chip is disposed in the through-hole, and
the encapsulant fills at least a portion of the through-hole.

14. The semiconductor package according to claim 13 ,
wherein the frame comprises:
a first build-up layer in contact with the first insulation layer;
a first wiring layer in contact with the first insulation layer and embedded in the first build-up layer;
a second wiring layer disposed on a side of the first build-up layer, opposite to a side in which the first wiring layer is embedded;
a second build-up layer disposed on the first build-up layer and covering the second wiring layer; and
a third wiring layer disposed on a side of the second build-up layer, opposite to a side in which the second wiring layer is embedded, and
the first to third wiring layers are electrically connected to the connection pad.

15. The semiconductor package according to claim 13 ,
wherein the frame comprises:
a core layer;
first and second wiring layers respectively disposed on both surfaces of the core layer;
first and second build-up layers respectively disposed on both surfaces of the core layer and respectively covering the first and second wiring layers;
a third wiring layer disposed on a side of the first build-up layer, opposite to a side in which the first wiring layer is embedded; and
a fourth wiring layer disposed on a side of the second build-up layer, opposite to a side in which the second wiring layer is embedded, and
wherein the first to fourth wiring layers are electrically connected to the connection pad.

16. The semiconductor package according to claim 1 , wherein the one or more of the openings penetrate through one continuous pattern of the first redistribution layer.

17. A semiconductor package comprising:
a semiconductor chip having a connection pad;
an encapsulant covering at least a portion of the semiconductor chip; and
a connection structure disposed on the semiconductor chip and the encapsulant,
wherein the connection structure comprises a first insulation layer, a redistribution layer disposed on the first insulation layer, and a second insulation layer disposed on the first insulation layer and covering the redistribution layer,
the redistribution layer has a plurality of openings each having a cross shape, and
a thickness of the redistribution layer is 10 μm or less.

18. The semiconductor package according to claim 17 , wherein one or more of the plurality of openings penetrate through one continuous pattern of the redistribution layer.

19. A semiconductor package comprising:
a semiconductor chip having a connection pad;
an encapsulant covering at least a portion of the semiconductor chip; and
a connection structure disposed on the semiconductor chip and the encapsulant,
wherein the connection structure comprises a first insulation layer, a first redistribution layer disposed on the first insulation layer, a second insulation layer disposed on the first insulation layer and covering the first redistribution layer, and a second redistribution layer disposed on the second insulation layer,
the first redistribution layer has a plurality of first openings each having a cross shape,
the second redistribution layer has a plurality of second openings each having a cross shape, and
in a plan view, the plurality of first openings and the plurality of second openings are spaced apart from each other.

20. The semiconductor package according to claim 19 , wherein one or more of the plurality of first openings penetrate through one continuous pattern of the first redistribution layer,
one or more of the plurality of second openings penetrate through one continuous pattern of second redistribution layer, and
in the plan view, the one continuous pattern of the first redistribution layer and the one continuous pattern of the second redistribution layer at least partially overlap with each other.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Daeyeun
• Jung Jaemok
• Kim Eunjin
• Kwon Chilwoo

Classifications

• H10W70/655

  Fan-out layouts · CPC title

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title