Fan-out semiconductor package

Patent metadata

Field	Value
Publication number	US-10312195-B2
Application number	US-201715819541-A
Country	US
Kind code	B2
Filing date	Nov 21, 2017
Priority date	Jul 14, 2017
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on the semiconductor chip and including a first redistribution layer electrically connected to the connection pads and a second redistribution layer electrically connected to the connection pads and disposed on the first redistribution layer. The first redistribution layer includes a first pattern having a plurality of degassing holes, the second redistribution layer includes a second pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width greater than the first line width, and the second line portion overlaps at least one of the plurality of degassing holes when being projected in a direction perpendicular to the active surface.

First claim

What is claimed is:

1. A semiconductor package comprising:
a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; and
a first connection member disposed on the active surface of the semiconductor chip, and including a first insulating layer disposed on the active surface of the semiconductor chip, a first redistribution layer made of an electrically conductive material and electrically connected to the connection pads through vias in the first insulating layer, a second insulating layer covering the first redistribution layer, and a second redistribution layer electrically connected to the connection pads through at least the first redistribution layer and being in contact with the second insulating layer,
wherein the first redistribution layer includes a first conductive pattern having a plurality of holes exposing portions of the first insulating layer, respectively,
the second insulating layer fills the plurality of holes and is in contact with the portions of the first insulating layers exposed by the plurality of holes,
when viewed in a direction perpendicular to the active surface, the second redistribution layer includes a second conductive pattern having a first line portion having a first line width and a second line portion extending from the first line portion and having a second line width greater than the first line width, and
the second line portion overlaps at least one of the plurality of holes when being projected in the direction perpendicular to the active surface.

2. The semiconductor package of claim 1 , wherein the first conductive pattern is a ground pattern and the second conductive pattern is a signal pattern.

3. The semiconductor package of claim 1 , wherein the first conductive pattern is a single integral pattern having the plurality of holes surrounded by an outer boundary of the first conductive pattern.

4. The semiconductor package of claim 3 , wherein the second conductive pattern extends across the first conductive pattern when being projected in the direction perpendicular to the active surface.

5. The semiconductor package of claim 1 , wherein the plurality of holes are degassing holes.

6. The semiconductor package of claim 1 , wherein when viewed in the direction perpendicular to the active surface, a line width of the second conductive pattern is changed from the first line width of the first line portion to the second line width of the second line portion before the second conductive pattern passes through a region in which the second line portion overlaps the at least one of the plurality of holes, and is changed from the second line width of the second line portion to the first line width of the first line portion after the second conductive pattern passes through the region.

7. The semiconductor package of claim 1 , wherein the first conductive pattern and the second conductive pattern include copper (Cu).

8. The semiconductor package of claim 1 , wherein the second insulating layer includes recesses recessed toward the plurality of holes, respectively.

9. The semiconductor package of claim 1 , further comprising:
a second connection member having a through-hole, in which the semiconductor chip is disposed; and
an encapsulant encapsulating at least portions of the semiconductor chip and the second connection member, and filling portions of the through-hole.

10. The semiconductor package of claim 9 , wherein the second connection member includes a third insulating layer, a first wiring layer in contact with the first connection member and embedded in the third insulating layer, and a second wiring layer disposed on the other surface of the third insulating layer opposing one surface of the third insulating layer in which the first wiring layer is embedded, and
the first and second wiring layers are electrically connected to the connection pads.

11. The semiconductor package of claim 10 , wherein the second connection member further includes a fourth insulating layer disposed on the third insulating layer and covering the second wiring layer and a third wiring layer disposed on the fourth insulating layer, and
the third wiring layer is electrically connected to the connection pads.

12. The semiconductor package of claim 10 , wherein a lower surface of the first wiring layer has a step with respect to a lower surface of the third insulating layer.

13. The semiconductor package of claim 9 , wherein the second connection member includes a third insulating layer, a first wiring layer and a second wiring layer disposed on opposite surfaces of the third insulating layer, respectively, a fourth insulating layer disposed on the third insulating layer and covering the first wiring layer, and a third wiring layer disposed on the fourth insulating layer, and
the first to third wiring layers are electrically connected to the connection pads.

14. The semiconductor package of claim 13 , wherein the second connection member further includes a fifth insulating layer disposed on the third insulating layer and covering the second wiring layer and a fourth wiring layer disposed on the fifth insulating layer, and
the fourth wiring layer is electrically connected to the connection pads.

15. The semiconductor package of claim 13 , wherein the third insulating layer has a thickness greater than that of the fourth insulating layer.

16. A semiconductor package comprising:
a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the semiconductor chip; and
a first connection member disposed on the active surface of the semiconductor chip, and including a first insulating layer disposed on the active surface of the semiconductor chip, a first redistribution layer made of an electrically conductive material and electrically connected to the connection pads through vias in the first insulating layer, a second insulating layer covering the first redistribution layer, and a second redistribution layer electrically connected to the connection pads through at least the first redistribution layer and being in contact with the second insulating layer,
wherein the first redistribution layer includes a first conductive pattern having a plurality of holes exposing portions of the first insulating layer, respectively, and a second conductive pattern disposed inside one of the plurality of holes,
the second insulating layer fills the plurality of holes and is in contact with the portions of the first insulating layers exposed by the plurality of holes,
the second distribution layer includes a third conductive pattern, and
the third conductive pattern overlaps with the second conductive pattern, when being projected in a direction perpendicular to the active surface.

17. The semiconductor package of claim 16 , wherein the second conductive pattern is spaced apart from the one of the plurality of holes.

18. The semiconductor package of claim 16 , wherein the one of the plurality of holes is separated into a plurality of sub-holes by the second conductive pattern.

19. A semiconductor package comprising:
a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the semiconductor chip; and
a first connection member disposed on the active surface of the semiconductor chip, and includ

Assignees

• Samsung Electro Mech

Inventors

• Lee Ji Hyun
• Kim Jin Gu
• Lee Chang Bae
• Kim Jin Su

Classifications

• H10W70/655

  Fan-out layouts · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W70/6528

  of the portions that connect to chips, wafers or package parts · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title