Resistor structures of integrated circuit devices including stacked transistors and methods of forming the same

Patent metadata

Field	Value
Publication number	US-12249603-B2
Application number	US-202217570920-A
Country	US
Kind code	B2
Filing date	Jan 7, 2022
Priority date	Oct 29, 2021
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

Resistor structures of stacked devices and methods of forming the same are provided. The, resistor structures may include a substrate, an upper semiconductor layer that may be spaced apart from the substrate in a vertical direction, a lower semiconductor layer that may be between the substrate and the upper semiconductor layer, and first and second resistor contacts that may be spaced apart from each other in a horizontal direction. At least one of the upper semiconductor layer, the lower semiconductor layer, and a portion of the substrate may contact the first and second resistor contacts.

First claim

What is claimed is:

1. A resistor structure comprising:
a substrate;
an upper semiconductor layer that is spaced apart from the substrate in a vertical direction;
a lower semiconductor layer that is between the substrate and the upper semiconductor layer and spaced apart in the vertical direction from the substrate and from the upper semiconductor layer;
an insulating layer that is between the upper semiconductor layer and the lower semiconductor layer; and
first and second resistor contacts that are spaced apart from each other in a horizontal direction,
wherein at least one of the upper semiconductor layer, the lower semiconductor layer, and a portion of the substrate contacts the first and second resistor contacts.

2. The resistor structure of claim 1 , wherein both the upper semiconductor layer and the lower semiconductor layer contact the first and second resistor contacts.

3. The resistor structure of claim 2 , wherein the portion of the substrate contacts the first and second resistor contacts.

4. The resistor structure of claim 1 , wherein the portion of the substrate is a first portion of the substrate, and the substrate further comprises a second portion,
the upper semiconductor layer is a first upper semiconductor layer, and the lower semiconductor layer is a first lower semiconductor layer, and
the resistor structure further comprises:
a second upper semiconductor layer that is spaced apart from the first upper semiconductor layer in the horizontal direction;
a second lower semiconductor layer that is between the substrate and the second upper semiconductor layer; and
a third resistor contact that is spaced apart from the second resistor contact in the horizontal direction,
wherein at least one of the second upper semiconductor layer, the second lower semiconductor layer, and the second portion of the substrate contacts the second and third resistor contacts.

5. The resistor structure of claim 4 , wherein both the second upper semiconductor layer and the second lower semiconductor layer contact the second and third resistor contacts.

6. The resistor structure of claim 5 , wherein the second portion of the substrate contacts the second and third resistor contacts.

7. The resistor structure of claim 1 , wherein the upper semiconductor layer is spaced apart from at least one of the first and second resistor contacts.

8. The resistor structure of claim 1 , wherein the lower semiconductor layer is spaced apart from at least one of the first and second resistor contacts.

9. The resistor structure of claim 1 , wherein the horizontal direction is a first horizontal direction, and
the resistor structure further comprises:
an upper thin semiconductor layer protruding from a side surface of the upper semiconductor layer in a second horizontal direction that is different from the first horizontal direction;
a lower thin semiconductor layer protruding from a side surface of the lower semiconductor layer in the second horizontal direction; and
a metal layer that is spaced apart from the upper semiconductor layer in the second horizontal direction, and a portion of the upper thin semiconductor layer or a portion of the lower thin semiconductor layer is in the metal layer.

10. The resistor structure of claim 1 , wherein the horizontal direction is a first horizontal direction,
the upper semiconductor layer is one of a pair of upper semiconductor layers that are spaced apart from each other in a second horizontal direction that is different from the first horizontal direction, and the lower semiconductor layer is one of a pair of lower semiconductor layers that are spaced apart from each other in the second horizontal direction, and
the resistor structure further comprises:
an upper thin semiconductor layer contacting the pair of upper semiconductor layers; and
a lower thin semiconductor layer contacting the pair of lower semiconductor layers.

11. An integrated circuit device comprising:
the resistor structure of claim 1 ; and
a stacked transistor structure comprising:
an upper transistor comprising an upper source/drain region; and
a lower transistor that is between the substrate and the upper transistor and comprises a lower source/drain region,

wherein the upper semiconductor layer and the upper source/drain region comprise a same material and have an equal thickness in the vertical direction, and the lower semiconductor layer and the lower source/drain region comprise a same material and have an equal thickness in the vertical direction.

12. A resistor structure comprising:
a substrate;
an upper semiconductor layer that is spaced apart from the substrate in a vertical direction;
a lower semiconductor layer that is between the substrate and the upper semiconductor layer;
an upper thin semiconductor layer protruding from a side surface of the upper semiconductor layer in a horizontal direction; and
a lower thin semiconductor layer protruding from a side surface of the lower semiconductor layer in the horizontal direction,
wherein the lower thin semiconductor layer is between the substrate and the upper thin semiconductor layer, and
wherein at least two of the upper semiconductor layer, the lower semiconductor layer, and a portion of the substrate are configured to function as respective resistors that are connected in parallel.

13. The resistor structure of claim 12 , wherein all of the upper semiconductor layer, the lower semiconductor layer, and the portion of the substrate are configured to function as respective resistors that are connected in parallel.

14. The resistor structure of claim 12 , wherein the horizontal direction is a first horizontal direction, and
the resistor structure further comprises first and second resistor contacts that are spaced apart from each other in a second horizontal direction that is different from the first horizontal direction, and
wherein the at least two of the upper semiconductor layer, the lower semiconductor layer, and the portion of the substrate contact the first and second resistor contacts.

15. The resistor structure of claim 12 , further comprising:
a metal layer that is spaced apart from the upper semiconductor layer in the horizontal direction, wherein a portion of the upper thin semiconductor layer or a portion of the lower thin semiconductor layer is in the metal layer.

16. A method of forming an integrated circuit device, the method comprising:
forming a resistor structure, wherein forming the resistor structure comprises:
forming a lower thin semiconductor layer and an upper thin semiconductor layer on a substrate, wherein the lower thin semiconductor layer is spaced apart from the substrate in a vertical direction and is between the substrate and the upper thin semiconductor layer;
forming a lower semiconductor layer by performing a first epitaxial growth process using the lower thin semiconductor layer as a first seed layer;
forming an upper semiconductor layer by performing a second epitaxial growth process using the upper thin semiconductor layer as a second seed layer; and
forming first and second resistor contacts that are spaced apart from each other in a horizontal direction and contact at least one of the upper semiconductor layer, the lower semiconductor layer, and a portion of the substrate.

17. The method of claim 16 , further comprising:
adding impurities to the portion of the substrate, wherein the portion of the substrate contacts the first and second resistor contacts.

18. The method of claim 16 , wherein the lower semiconduct

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hong Byounghak
• Yun Seungchan
• Hwang Inchan
• Park Hyoeun
• Seo Kang-Ill

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W44/401 Primary

  Resistive arrangements (H10W44/20, H10W42/80 take precedence) · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D84/209

  of only resistors · CPC title

• H10D1/47 Primary

  Resistors having no potential barriers · CPC title